SLLS888B June   2008  – October 2016 SN65HVD1050A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Electrical Characteristics: Driver
    7. 7.7  Electrical Characteristics: Receiver
    8. 7.8  Switching Characteristics: Device
    9. 7.9  Switching Characteristics: Driver
    10. 7.10 Switching Characteristics: Receiver
    11. 7.11 S Pin Characteristics
    12. 7.12 VREF Pin Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TXD Dominant State Time-Out
      2. 9.3.2 Thermal Shutdown
      3. 9.3.3 Undervoltage Lockout and Unpowered Device
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Silent Mode
      2. 9.4.2 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Using the Device With 3.3-V Microcontrollers
      2. 10.1.2 Using SPLIT (VREF) With Split Termination
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 10.2.1.2 CAN Termination
        3. 10.2.1.3 Loop Propagation Delay
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ESD Protection
        2. 10.2.2.2 Transient Voltage Suppresser (TVS) Diodes
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
VCC Supply voltage(2) –0.3 6 V
Voltage at any bus terminal (CANH, CANL, Vref) –27 40 V
IO Receiver output current 20 mA
VI Voltage input, ISO 7637 transient pulse(3) (CANH, CANL) –150 100 V
VI Voltage input (TXD, S) –0.3 6 V
TJ Junction temperature –40 150 °C
PD Average power dissipation VCC = 5 V, TJ = 27°C, RL = 60 Ω, S at 0 V,
Input to TXD at 500 kHz, 50% duty cycle square wave,
CL at RXD = 15 pF		 112 mW
VCC = 5.5 V, TJ = 130°C, RL = 45 Ω, S at 0 V,
Input to TXD at 500 kHz, 50% duty cycle square wave,
CL at RXD = 15 pF		 170
Thermal shutdown temperature 190 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with ISO 7637 test pulses 1, 2, 3a, 3b per IBEE system level test (Pulse 1 = –100 V, Pulse 2 = 100 V, Pulse 3a = –150 V, Pulse 3b = 100 V). If dc may be coupled with ac transients, externally protect the bus pins within the absolute maximum voltage range at any bus terminal. This device has been tested with dc bus shorts to 40 V with leading common-mode chokes. If common-mode chokes are used in the system and the bus lines may be shorted to dc, ensure that the choke type and value in combination with the node termination and shorting voltage either will not create inductive flyback outside of voltage maximum specification or use an external transient-suppression circuit to protect the transceiver from the inductive transients.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge(3) Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)		 All pins except 6 and 7 ±4000 V
Pins 6 and 7(4) ±12000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)(5) ±1500
Machine model(6) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) All typical values at 25°C.
(4) Test method based upon JEDEC Standard 22 Test Method A114E, CANH and CANL bus pins stressed with respect to each other and GND.
(5) Tested in accordance JEDEC Standard 22, Test Method C101C.
(6) Tested in accordance JEDEC Standard 22, Test Method A115A.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 4.75 5.25 V
VI or VIC Voltage at any bus terminal (separately or common mode) –12 12 V
VIH High-level input voltage TXD, S 2 5.25 V
VIL Low-level input voltage TXD, S 0 0.8 V
VID Differential input voltage –6 6 V
IOH High-level output current Driver –70 mA
Receiver –2
IOL Low-level output current Driver 70 mA
Receiver 2
TA Operating free-air temperature See Thermal Information. –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) SN65HVD1050A-Q1 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance(2) Low-K thermal resistance(3) 211 °C/W
High-K thermal resistance(3) 131
RθJC(top) Junction-to-case (top) thermal resistance 79 °C/W
RθJB Junction-to-board thermal resistance 53 °C/W
ψJT Junction-to-top characterization parameter 8 °C/W
ψJB Junction-to-board characterization parameter 49.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 79 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction temperature (TJ) is calculated using the following TJ = TA + (PD × RθJA).
(3) Tested in accordance with the Low-K (EIA/JESD51-3) or High-K (EIA/JESD51-7) thermal metric definitions for leaded surface-mount packages.

7.5 Electrical Characteristics: Supply Current

over recommended operating conditions, TA = –40 to 125°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC 5-V supply current Silent mode S at VCC, VI= VCC 6 10 mA
Dominant VI = 0 V, 60-Ω load, S at 0 V 50 70
Recessive VI = VCC, No load, S at 0 V 6 10
(1) All typical values are at 25°C with a 5-V supply.

7.6 Electrical Characteristics: Driver

over recommended operating conditions, TA = –40 to 125°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO(D) Bus output voltage (dominant) CANH VI = 0 V, S at 0 V, RL = 60 Ω, See Figure 3 and Figure 4 2.9 3.4 4.5 V
CANL 0.8 1.5
VO(R) Bus output voltage (recessive) VI = 3 V, S at 0 V, RL = 60 Ω, See Figure 3 and Figure 4 2 2.3 3 V
VOD(D) Differential output voltage (dominant) VI = 0 V, RL = 60 Ω, S at 0 V, See Figure 3, Figure 4, and Figure 5 1.5 3 V
VI = 0 V, RL = 45 Ω, S at 0 V, See Figure 3, Figure 4, and Figure 5 1.4 3 V
VOD(R) Differential output voltage (recessive) VI = 3 V, S at 0 V, See Figure 3 and Figure 4 –0.012 0.012 V
VI = 3 V, S at 0 V, No Load –0.5 0.05
VOC(ss) Steady state common-mode output voltage S at 0 V, Figure 10 2 2.3 3 V
ΔVOC(ss) Change in steady-state common-mode output voltage 30 mV
IIH High-level input current, TXD input VI at VCC –2 2 µA
IIL Low-level input current, TXD input VI at 0 V –50 –10
IO(off) Power-off TXD output current VCC at 0 V, TXD at 5 V 1
IOS(ss) Short-circuit steady-state output current VCANH = –12 V, CANL open, See Figure 13 –105 –72 mA
VCANH = 12 V, CANL open, See Figure 13 0.36 1
VCANL = –12 V, CANH open, See Figure 13 –1 –0.5
VCANL = 12 V, CANH open, See Figure 13 71 105
CO Output capacitance See receiver input capacitance.
(1) All typical values are at 25°C with a 5-V supply.

7.7 Electrical Characteristics: Receiver

over recommended operating conditions, TA = –40 to 125°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage S at 0 V, See Table 1 800 900 mV
VIT– Negative-going input threshold voltage S at 0 V, See Table 1 500 650 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100 125 mV
VOH High-level output voltage IO = –2 mA, See Figure 8 4 4.6 V
VOL Low-level output voltage IO = 2 mA, See Figure 8 0.2 0.4 V
II(off) Power-off bus input current CANH or CANL = 5 V,
Other pin at 0 V,
VCC at 0 V, TXD at 0 V		 165 250 µA
IO(off) Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 µA
CI Input capacitance to ground (CANH or CANL) TXD at 3 V,
VI = 0.4 sin (4E6πt) + 2.5 V		 13 pF
CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) 6 pF
RID Differential input resistance TXD at 3 V, S at 0 V 30 80 kΩ
RIN Input resistance (CANH or CANL) TXD at 3 V, S at 0 V 15 30 40 kΩ
RI(m) Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] × 100%		 V(CANH) = V(CANL) –3% 0% 3%
(1) All typical values are at 25°C with a 5-V supply.

7.8 Switching Characteristics: Device

over recommended operating conditions, TA = –40 to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(LOOP1) Total loop delay, driver input to receiver output,
recessive to dominant		 S at 0 V, See Figure 11 90 230 ns
td(LOOP2) Total loop delay, driver input to receiver output,
dominant to recessive		 S at 0 V, See Figure 11 90 230 ns

7.9 Switching Characteristics: Driver

over recommended operating conditions, TA = –40 to 125°C (unless otherwise noted)(1)
MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high level output S at 0 V, See Figure 6 25 65 120 ns
tPHL Propagation delay time, high-to-low level output S at 0 V, See Figure 6 25 45 120 ns
tr Differential output signal rise time S at 0 V, See Figure 6 25 ns
tf Differential output signal fall time S at 0 V, See Figure 6 50 ns
ten Enable time from silent mode to dominant See Figure 9 1 µs
t(dom) Dominant time out(2) ↓VI, See Figure 12 300 450 700 µs
(1) All typical values are at 25°C with a 5-V supply.
(2) The TXD dominant time out (t(dom)) will disable the driver of the transceiver once the TXD has been dominant longer than t(dom)which will release the bus lines to recessive preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults locking the bus dominant it will limit the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case where five successive dominant bits are followed immediately by an error frame. This along with the t(dom) minimum will limit the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t(dom) = = 11 bits / 300 µs = 37 kbps.

7.10 Switching Characteristics: Receiver

over recommended operating conditions, TA = –40 to 125°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output S at 0 V or VCC, See Figure 8 60 100 130 ns
tPHL Propagation delay time, high-to-low-level output 45 70 130 ns
tr Output signal rise time 8 ns
tf Output signal fall time 8 ns
(1) All typical values are at 25°C with a 5-V supply.

7.11 S Pin Characteristics

over recommended operating conditions, TA = –40 to 125°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High level input current S at 2 V 20 40 70 µA
IIL Low level input current S at 0.8 V 5 20 30 µA
(1) All typical values are at 25°C with a 5-V supply.

7.12 VREF Pin Characteristics

over recommended operating conditions, TA = –40 to 125°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Reference output voltage –50 µA < IO < 50 µA 0.4 VCC 0.5 VCC 0.6 VCC V
(1) All typical values are at 25°C with a 5-V supply.

7.13 Typical Characteristics

SN65HVD1050A-Q1 D001_SLLS994.gif
S = 0 V RL = 60 Ω TXD Input 125 kHz
Figure 1. Driver Differential Voltage vs Supply Voltage
SN65HVD1050A-Q1 D002_SLLS994.gif
Figure 2. Dominant Driver Differential Voltage
vs Free-Air Temperature