JAJSND7P
February 2002 – February 2022
SN65HVD10
,
SN65HVD11
,
SN65HVD12
,
SN75HVD12
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Driver Electrical Characteristics
7.6
Receiver Electrical Characteristics
7.7
Power Dissipation Characteristics
7.8
Driver Switching Characteristics
7.9
Receiver Switching Characteristics
7.10
Dissipation Ratings
7.11
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.4
Device Functional Modes
9.4.1
Low-Power Standby Mode
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.1.1
Data Rate and Bus Length
10.2.1.2
Stub Length
10.2.1.3
Bus Loading
10.2.1.4
Receiver Fail-safe
10.2.2
Detailed Design Procedure
10.2.3
Application Curve
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
12.3
Thermal Considerations
12.3.1
Thermal Characteristics of IC Packages
13
Device and Documentation Support
13.1
Device Support
13.2
Related Links
13.3
Receiving Notification of Documentation Updates
13.4
サポート・リソース
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
P|8
MPDI001B
サーマルパッド・メカニカル・データ
発注情報
jajsnd7p_oa
jajsnd7p_pm
8
Parameter Measurement Information
Figure 8-1
Driver V
OD
Test Circuit and Voltage and Current Definitions
Figure 8-2
Driver V
OD
With Common-Mode Loading Test Circuit
Input: PRR = 500 kHz, 50% Duty Cycle, t
r
< 60 ns, t
f
< 6 ns Z
O
= 50 Ω
Figure 8-3
Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
< 60 ns, t
f
< 6 ns Z
O
= 50 Ω
Figure 8-4
Driver Switching Test Circuit and Voltage Waveforms
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
< 60 ns, t
f
< 6 ns Z
O
= 50 Ω
Figure 8-5
Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
< 60 ns, t
f
< 6 ns Z
O
= 50 Ω
Figure 8-6
Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
The time t
PZL(x)
is the measure from DE to V
OD
(x). V
OD
is valid when it is greater than 1.5 V.
Figure 8-7
Driver Enable Time from DE to V
OD
Figure 8-8
Receiver Voltage and Current Definitions
Figure 8-9
Receiver Switching Test Circuit and Voltage Waveforms
Figure 8-10
Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
Figure 8-11
Receiver Enable Time From Standby (Driver Disabled)
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 8-12
Test Circuit, Transient Over Voltage Test
Figure 8-13
Equivalent Input and Output Schematic Diagrams