JAJSGX8C April   2002  – February 2019 SN65LVDT14 , SN65LVDT41

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      SN65LVDT41 の機能図
      2.      SN65LVDT14 の機能図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     SN65LVDT41 Pin Functions
    2.     SN65LVDT14 Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Receiver Electrical Characteristics
    6. 7.6  Driver Electrical Characteristics
    7. 7.7  Device Electrical Characteristics
    8. 7.8  Receiver Switching Characteristics
    9. 7.9  Driver Switching Characteristics
    10. 7.10 Typical Characteristics
      1. 7.10.1 Receiver
      2. 7.10.2 Driver
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 SN65LVDTxx Driver and Receiver Functionality
      2. 9.3.2 Integrated Termination
      3. 9.3.3 SN65LVDTxx Equivalent Circuits
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Extending a Serial Peripheral Interface Using LVDS Signaling Over Differential Transmission Cables
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 SPI Propagation Delay Limitations
        2. 10.2.2.2 Interconnecting Media
        3. 10.2.2.3 Input Fail-Safe Biasing
        4. 10.2.2.4 Power Decoupling Recommendations
        5. 10.2.2.5 PCB Transmission Lines
        6. 10.2.2.6 Probing LVDS Transmission Lines on PCB
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
      6. 12.1.6 Decoupling
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 関連リンク
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

12.1.2 Dielectric Type and Board Construction

The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or an equivalent, usually provides adequate performance for use with LVDS signals. If rise or fall times of LVCMOS/LVTTL signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350 or Nelco N4000-13, may be desired. Once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. The following set of guidelines were developed experimentally through several designs involving LVDS devices:

  • Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
  • All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
  • Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
  • Solder mask over bare copper with solder hot-air leveling