JAJSO56E December   1982  – February 2022 SN54HC166 , SN74HC166

PRODUCTION DATA  

  1. 1 特長
  2. 2 概要
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6.     11
    7. 5.6 Switching Characteristics
    8. 5.7 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • DB|16
  • NS|16
  • N|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

5.5 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted)
VCC(V) TA = 25°C SN54HC166 SN74HC166 UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 2 6 4.2 5 MHz
4.5 31 21 25
6 36 25 29
tw Pulse duration CLR low 2 100 150 125 ns
4.5 20 30 25
6 17 26 21
CLK high or low 2 80 120 100
4.5 16 24 20
6 14 20 17
tsu Setup time SH/LD high before CLK­↑ 2 145 220 180 ns
4.5 29 44 36
6 25 38 31
SER before CLK­↑ 2 80 120 100
4.5 16 24 20
6 14 20 17
CLK INH low before CLK­↑ 2 100 150 125
4.5 20 30 25
6 17 26 21
Data before CLK­↑ 2 80 120 100
4.5 16 24 20
6 14 20 17
CLR inactive before CLK­↑ 2 40 60 50
4.5 8 12 10
6 7 10 9
th Hold time SH/LD high after CLK­↑ 2 0 0 0 ns
4.5 0 0 0
6 0 0 0
SER after CLK­↑ 2 5 5 5
4.5 5 5 5
6 5 5 5
CLK INH high after CLK­↑ 2 0 0 0
4.5 0 0 0
6 0 0 0
Data after CLK­↑ 2 5 5 5
4.5 5 5 5
6 5 5 5