JAJSPN6A
january 2023 – august 2023
SN74LV165B-EP
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements, VCC = 2.5 V ± 0.2 V
6.7
Timing Requirements, VCC = 3.3 V ± 0.3 V
6.8
Timing Requirements, VCC = 5 V ± 0.5 V
6.9
Switching Characteristics, VCC = 2.5 V ± 0.2 V
6.10
Switching Characteristics, VCC = 3.3 V ± 0.3 V
6.11
Switching Characteristics, VCC = 5 V ± 0.5 V
6.12
Operating Characteristics
6.13
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS Push-Pull Outputs
8.3.2
Latching Logic
8.3.3
Partial Power Down (Ioff)
8.3.4
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Power Considerations
9.2.2
Input Considerations
9.2.3
Output Considerations
9.2.4
Detailed Design Procedure
9.2.5
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
PW|16
サーマルパッド・メカニカル・データ
発注情報
jajspn6a_oa
9.4
Layout