JAJSQP1J april   1999  – july 2023 SN74LV4040A

PRODMIX  

  1.   1
  2. 1特長
  3. 2概要
  4. 3Revision History
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
    7. 5.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 5.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 5.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    10. 5.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 5.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 5.12 Noise Characteristics
    13. 5.13 Operating Characteristics
  7. 6Parameter Measurement Information
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • DB|16
  • NS|16
  • N|16
  • RGY|16
  • D|16
  • DGV|16
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits, counter controls, and frequency-dividing circuits.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.