JAJSTF3T January   1993  – May 2024 SN54LVC00A , SN74LVC00A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions, SN54LVC00A
    4. 5.4  Recommended Operating Conditions, SN74LVC00A
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics, SN54LVC00A
    7. 5.7  Electrical Characteristics, SN74LVC00A
    8. 5.8  Switching Characteristics, SN54LVC00A
    9. 5.9  Switching Characteristics, SN74LVC00A
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diodes
      4. 7.3.4 Over-voltage Tolerant Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3.     Power Supply Recommendations
    4. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Links
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
      1. 9.3.1 Community Resources
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 1046
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|14
  • RGY|14
  • DB|14
  • PW|14
  • BQA|14
  • NS|14
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

SN54LVC00A SN74LVC00A SN54LVC00A J or W Package; SN74LVC00A D, DB, NS, or PW Package14-Pin CDIP, CFPSOIC, SSOP, SO, or TSSOP(Top View)Figure 4-1 SN54LVC00A J or W Package; SN74LVC00A D, DB, NS, or PW Package14-Pin CDIP, CFP
SOIC, SSOP, SO, or TSSOP(Top View)
SN54LVC00A SN74LVC00A SN54LVC00A FK Package20-Pin LCCC(Top View)
NC - No internal connection
Figure 4-2 SN54LVC00A FK Package20-Pin LCCC(Top View)
SN54LVC00A SN74LVC00A SN74LVC00A BQA or RGY Package14-Pin WQFN or VQFN(Top View) Figure 4-3 SN74LVC00A BQA or RGY Package14-Pin WQFN or VQFN(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME SN74LVC00A SN54LVC00A
D, DB, NS, PW BQA, RGY J, W FK
1A 1 1 1 2 I Gate 1 input
1B 2 2 2 3 I Gate 1 input
1Y 3 3 3 4 O Gate 1 output
2A 4 4 4 6 I Gate 2 input
2B 5 5 5 8 I Gate 2 input
2Y 6 6 6 9 O Gate 2 output
GND 7 7 7 10 I Ground Pin
3Y 8 8 8 12 O Gate 3 output
3A 9 9 9 13 I Gate 3 input
3B 10 10 10 14 I Gate 3 input
4Y 11 11 11 16 O Gate 4 output
4A 12 12 12 18 I Gate 4 input
4B 13 13 13 19 I Gate 4 input
VCC 14 14 14 20 — Positive supply
NC — — — 1 — No Connection
5
7
11
15
17