JAJST37T March   1994  – May 2024 SN74LVC126A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MINNOMMAXUNIT
VCCSupply voltageOperating1.653.6V
Data retention only1.5
VIHHigh-level input voltageVCC = 1.65 V to 1.95 V0.65 × VCCV
VCC = 2.3 V to 2.7 V1.7
VCC = 2.7 V to 3.6 V2
VILLow-level input voltageVCC = 1.65 V to 1.95 V0.35 × VCCV
VCC = 2.3 V to 2.7 V0.7
VCC = 2.7 V to 3.6 V0.8
VIInput voltage05.5V
VOOutput voltage0VCCV
IOHHigh-level output currentVCC = 1.65 V–4mA
VCC = 2.3 V–8
VCC = 2.7 V–12
VCC = 3 V–24
IOLLow-level output currentVCC = 1.65 V4mA
VCC = 2.3 V8
VCC = 2.7 V12
VCC = 3 V24
Δt/ΔvInput transition rise or fall rate10ns/V
TAOperating free-air temperature–40125°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs.