JAJSPC9E September   2006  – December 2022 SN74LVC1T45-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: VCCA = 1.8 V ±0.15 V
    7. 6.7  Switching Characteristics: VCCA = 2.5 V ±0.2 V
    8. 6.8  Switching Characteristics: VCCA = 3.3 V ±0.3 V
    9. 6.9  Switching Characteristics: VCCA = 5 V ±0.5 V
    10. 6.10 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1.      Application and Implementation
        1. 8.1 Application Information
          1. 8.1.1 Enable Times
        2. 8.2 Typical Applications
          1. 8.2.1 Unidirectional Logic Level-Shifting Application
            1. 8.2.1.1 Design Requirements
            2. 8.2.1.2 Detailed Design Procedure
            3. 8.2.1.3 Application Curves
          2. 8.2.2 Bidirectional Logic Level-Shifting Application
            1. 8.2.2.1 Detailed Design Procedure
            2. 8.2.2.2 Application Curves
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DCK|6
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Bidirectional Logic Level-Shifting Application

Figure 8-3 shows the SN74LVC1T45-Q1 being used in a bidirectional logic level-shifting application. Because the SN74LVC1T45-Q1 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.

GUID-D8063DAA-54E5-4134-B8D9-20E5A825323D-low.gifFigure 8-3 Bidirectional Logic Level-Shifting Application