JAJSKB1N December   2003  – June 2024 SN74LVC1T45

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics (VCCA = 1.8V ± 0.15V)
    7. 5.7  Switching Characteristics (VCCA = 2.5V ± 0.2V)
    8. 5.8  Switching Characteristics (VCCA = 3.3V ± 0.3V)
    9. 5.9  Switching Characteristics (VCCA = 5V ±0.5V)
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65V to 5.5V Power-Supply Range
      2. 7.3.2 Support High Speed Translation
      3. 7.3.3 Ioff Supports Partial Power-Down Mode Operation
      4. 7.3.4 Balanced High-Drive CMOS Push-Pull Outputs
      5. 7.3.5 Glitch-Free Power Supply Sequencing
      6. 7.3.6 Vcc Isolation
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Unidirectional Logic Level-Shifting Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bidirectional Logic Level-Shifting Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Enable Times
        3. 8.2.2.3 Application Curve
    3.     42
    4. 8.3 Power Supply Recommendations
    5. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

SN74LVC1T45 DBV Package,6-Pin SOT-23(Top View)Figure 4-1 DBV Package,6-Pin SOT-23(Top View)
SN74LVC1T45 DRL Package,6-Pin SOT(Top View)Figure 4-3 DRL Package,6-Pin SOT(Top View)
SN74LVC1T45 DCK Package,6-Pin SC70(Top View)Figure 4-2 DCK Package,6-Pin SC70(Top View)
SN74LVC1T45 DPK Package,6-Pin USON(Top View)Figure 4-4 DPK Package,6-Pin USON(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME DBV, DCK, DRL, DPK
VCCA 1 P SYSTEM-1 supply voltage (1.65V to 5.5V)
GND 2 G Device GND
A 3 I/O Output level depends on VCC1 voltage.
B 4 I/O Input threshold value depends on VCC2 voltage.
DIR 5 I GND (low level) determines B-port to A-port direction.
VCCB 6 P SYSTEM-2 supply voltage (1.65V to 5.5V)
(1) P = power, G = ground, I/O = input and output, I = input
SN74LVC1T45 YZP Package,6-Pin DSBGA(Bottom View) Figure 4-5 YZP Package,6-Pin DSBGA(Bottom View)
Legend
Power Input
Input or Output Ground
Table 4-2 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
A1 VCCA P SYSTEM-1 supply voltage (1.65V to 5.5V)
A2 VCCB P SYSTEM-2 supply voltage (1.65V to 5.5V)
B1 GND G Device GND
B2 DIR I GND (low level) determines B-port to A-port direction.
C1 A I/O Output level depends on VCC1 voltage.
C2 B I/O Input threshold value depends on VCC2 voltage.
(1) P = power, G = ground, I/O = input and output, I = input