SCES201N April   1999  – September 2015 SN74LVC2G32

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DCU|8
  • YZP|8
  • DCT|8
サーマルパッド・メカニカル・データ
発注情報

8 Detailed Description

8.1 Overview

The SN74LVC2G32 provides two logical OR gates per device and each gate has two inputs. Both input paths use identical circuitry for matching propagation delays. Supply voltage from 1.65 V to 5.5 V is supported.

8.2 Functional Block Diagram

SN74LVC2G32 LD_CES201.gif Figure 3. Logic Diagram (Positive Logic)

8.3 Feature Description

The SN74LVC2G32 inputs per gate can accept up to 5.5 V regardless of VCC.

8.4 Device Functional Modes

Table 1 lists the functional modes for the SN74LVC2G32.

Table 1. Function Table (Each Gate)(1)

INPUTS OUTPUT
Y
A B
H X H
X H H
L L L
(1) Y = A + B in positive logic.