SCBS778B November   2003  – June 2016 SN74LVTH16373-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements (I Version)
    7. 6.7  Switching Characteristics (I Version)
    8. 6.8  Timing Requirements (M Version)
    9. 6.9  Switching Characteristics (M Version)
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DGG or DL Package
48-Pin TSSOP or SSOP
Top View
SN74LVTH16373-EP po_DGG_DL_scbs778.gif
GQL Package
56-Pin BGA MICROSTAR JUNIOR
Top View
SN74LVTH16373-EP po_bga_scbs778.gif

Table 1. Pin Assignments(1)

1 2 3 4 5 6
A 1OE NC NC NC NC 1LE
B 1Q2 1Q1 GND GND 1D1 1D2
C 1Q4 1Q3 VCC VCC 1D3 1D4
D 1Q6 1Q5 GND GND 1D5 1D6
E 1Q8 1Q7 1D7 1D8
F 2Q1 2Q2 2D2 2D1
G 2Q3 2Q4 GND GND 2D4 2D3
H 2Q5 2Q6 VCC VCC 2D6 2D5
J 2Q7 2Q8 GND GND 2D8 2D7
K 2OE NC NC NC NC 2LE
(1) NC − No internal connection.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
1Dn(1) 37, 38, 49, 41, 43, 44, 46, 47 I Data input pins
1LE 48 I Latch enable pin to control 1Qn output states
1OE 1 I Active low enable pin for 1Qn pins
1Qn(1) 2, 3, 5, 6, 8, 9, 11, 12 O Output pins
2Dn(1) 26, 27, 29, 30, 32, 33, 35, 36 I Data input pins
2LE 25 I Latch enable pin to control 2Qn output states
2Qn(1) 13, 14, 16, 17, 19, 20, 22, 23 O Output pins
2OE 24 I Active low enable pin for 2Qn pins
GND 4, 10, 15, 21, 28, 34, 39, 45 — Ground
VCC 7, 18, 31, 42 I Power supply input for internal circuits
(1) "n" denotes numbering (1 to 8) for data input and output pins.