SLLS980E June 2009 – November 2016 SN75LVDS83A
PRODUCTION DATA.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLKIN | 31 | I | CMOS with pulldown; input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL. |
CLKOUTM | 40 | O | Differential LVDS pixel clock output. Output is high-impedance when SHTDN is pulled low (de-asserted). |
CLKOUTP | 39 | O | |
CLKSEL | 17 | I | CMOS with pulldown; selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger (CLKSEL = VIL). |
D0 | 51 | I | CMOS with pulldown; data inputs. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive). For input bit assignment, see Figure 14 to Figure 17 for details. Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND. |
D1 | 52 | I | |
D2 | 54 | I | |
D3 | 55 | I | |
D4 | 56 | I | |
D5 | 2 | I | |
D6 | 3 | I | |
D7 | 4 | I | |
D8 | 6 | I | |
D9 | 7 | I | |
D10 | 8 | I | |
D11 | 10 | I | |
D12 | 11 | I | |
D13 | 12 | I | |
D14 | 14 | I | |
D15 | 15 | I | |
D16 | 16 | I | |
D17 | 18 | I | |
D18 | 19 | I | |
D19 | 20 | I | |
D20 | 22 | I | |
D21 | 23 | I | |
D22 | 24 | I | |
D23 | 25 | I | |
D24 | 27 | I | |
D25 | 28 | I | |
D26 | 30 | I | |
D27 | 50 | I | |
GND | 5, 23, 21, 29, 43, 49, 53 |
P | Supply ground for VCC, LVDSVCC, and PLLVCC(2) |
LVDSVCC | 44 | P | 3.3-V LVDS output analog supply(2) |
PLLVCC | 34 | P | 3.3-V PLL analog supply(2) |
SHTDN | 32 | I | CMOS with pulldown; device shut down; pull low (deassert) to shut down the device (low power, resets all registers) and high (assert) for normal operation. |
VCC | 1, 9, 26 | P | 3.3-V digital supply voltage(2) |
Y0M | 48 | O | Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted). |
Y0P | 47 | O | Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted). |
Y1M | 46 | O | Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted). |
Y1P | 45 | O | Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted). |
Y2M | 42 | O | Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted). |
Y2P | 41 | O | Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted). |
Y3M | 38 | O | Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (deasserted). Note: If the application only requires 18-bit color, this output can be left open. |
Y3P | 37 | O | Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (deasserted). Note: If the application only requires 18-bit color, this output can be left open. |