SLASF32 December   2023 TAD5142

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Analog Output Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 DAC Signal-Chain
        1. 7.3.6.1 Configurable Digital Interpolation Filters
          1. 7.3.6.1.1 Linear Phase Filters
            1. 7.3.6.1.1.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.1.1.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.1.1.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.1.1.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.1.1.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.1.1.6 Sampling Rate: 384 kHz or 352.8 kHz
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.3 Detailed Design Procedure

This section describes the necessary steps to configure the TAD5142 for this specific application.

  1. Apply power to the device:
    1. Power up the IOVDD and AVDD power supplies
    2. Wait for at least 1ms to allow the device to initialize the internal registers.
    3. The device now goes into sleep mode (low-power mode < 10 µA)
  2. Configure the Mode Pins as per the system requirements:
    1. Select the ASI Mode by pulling up to AVDD or down to VSS; MD0 Pin. MD0 should be grounded for this use case.
    2. Pull Up to IOVDD or Pull down to VSS on MD1 to MD5 Pin as per the reuqired configuration. All the Pins are grounded for this use case.
  3. Applying the ASI Clocks will wake up the device (BCLK and FSYNC)
  4. To put th device back in sleep mode, Stop the clocks:
    1. Wait at least 100 ms to allow the device to complete the shutdown sequence
    2. Change the Mode configuration by changing MD0 to MD6 as per requirement
  5. Repeat step 4 and step 5 as required for mode transitions