JAJSPM3D July   2010  – January 2023 TCA6424A

PRODUCTION DATA  

  1. 特長
  2. 概要
  3. Revision History
  4. Description (continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Translation
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 I2C Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Address
    5. 8.5 Programming
      1. 8.5.1 Power-On Reset
      2. 8.5.2 Reset Input ( RESET)
      3. 8.5.3 Interrupt Output ( INT)
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Writes
        2. 8.5.4.2 Reads
    6. 8.6 Register Maps
      1. 8.6.1 Control Register and Command Byte
      2. 8.6.2 Register Descriptions
  9. Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Detailed Design Procedure
        1. 9.1.1.1 Minimizing ICC When I/Os Control LEDs
    2. 9.2 Power Supply Recommendation
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 商標
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Register Descriptions

The Input Port registers (registers 0, 1 and 2) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes to these registers have no effect. The default value (X) is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register will be accessed next.

Table 8-5 Registers 0, 1 and 2 (Input Port Registers)
BITI-07I-06I-05I-04I-03I-02I-01I-00
DEFAULTXXXXXXXX
BITI-17I-16I-15I-14I-13I-12I-11I-10
DEFAULTXXXXXXXX
BITI-27I-26I-25I-24I-23I-22I-21I-20
DEFAULTXXXXXXXX

The Output Port registers (registers 4, 5 and 6) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value.

Table 8-6 Registers 4, 5 and 6 (Output Port Registers)
BITO-07O-06O-05O-04O-03O-02O-01O-00
DEFAULT11111111
BITO-17O-16O-15O-14O-13O-12O-11O-10
DEFAULT11111111
BITO-27O-26O-25O-24O-23O-22O-21O-20
DEFAULT11111111

The Polarity Inversion registers (registers 8, 9 and 10) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Table 8-7 Registers 8, 9 and 10 (Polarity Inversion Registers)
BITP-07P-06P-05P-04P-03P-02P-01P-00
DEFAULT00000000
BITP-17P-16P-15P-14P-13P-12P-11P-10
DEFAULT00000000
BITP-27P-26P-25P-24P-23P-22P-21P-20
DEFAULT00000000

The Configuration registers (registers 12, 13 and 14) configure the direction of the I/O pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output.

Table 8-8 Registers 12, 13 and 14 (Configuration Registers)
BITC-07C-06C-05C-04C-03C-02C-01C-00
DEFAULT11111111
BITC-17C-16C-15C-14C-13C-12C-11C-10
DEFAULT11111111
BITC-27C-26C-25C-24C-23C-22C-21C-20
DEFAULT11111111