JAJSOW0A July   2022  – July 2023 TDP1204

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  4-Level Inputs
      2. 8.2.2  I/O Voltage Level Selection
      3. 8.2.3  HPD_OUT
      4. 8.2.4  Lane Control
      5. 8.2.5  Swap
      6. 8.2.6  Linear and Limited Redriver
      7. 8.2.7  Main Link Inputs
      8. 8.2.8  Receiver Equalizer
      9. 8.2.9  CTLE Bypass
      10. 8.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 8.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 8.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 8.2.12 Input Signal Detect
      13. 8.2.13 Main Link Outputs
        1. 8.2.13.1 Transmitter Bias
        2. 8.2.13.2 Transmitter Impedance Control
        3. 8.2.13.3 TX Slew Rate Control
        4. 8.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 8.2.13.5 TX Swing Control
      14. 8.2.14 DDC Buffer
      15. 8.2.15 HDMI DDC Capacitance
      16. 8.2.16 DisplayPort
    3. 8.3 Device Functional Modes
      1. 8.3.1 MODE Control
        1. 8.3.1.1 I2C Mode (MODE = "F")
        2. 8.3.1.2 Pin Strap Modes
          1. 8.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 8.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ and DDC Buffer Enabled
          3. 8.3.1.2.3 Pin-Strap HDMI 2.1 Function (MODE = "1"): Flexible RX EQ and DDC Buffer Enabled
          4. 8.3.1.2.4 Pin-Strap HDMI 2.1 Function (MODE = "R"): Flexible Rx EQ and DDC Buffer Disabled
      2. 8.3.2 DDC Snoop Feature
        1. 8.3.2.1 HDMI Type
        2. 8.3.2.2 HDMI 2.1 FRL Snoop
      3. 8.3.3 Low Power States
    4. 8.4 Programming
      1. 8.4.1 Pseudocode Examples
        1. 8.4.1.1 HDMI 2.1 Source Example with DDC Snoop and DDC Buffer Enabled
        2. 8.4.1.2 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
      2. 8.4.2 TDP1204 I2C Address Options
      3. 8.4.3 I2C Target Behavior
    5. 8.5 Register Maps
      1. 8.5.1 TDP1204 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Source-Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pre-Channel (LAB)
        2. 9.2.2.2 Post-Channel (LCD)
        3. 9.2.2.3 Common Mode Choke
        4. 9.2.2.4 ESD Protection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Sink-Side Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedures
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Supply Decoupling
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントのサポート
      1. 10.1.1 関連資料
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1 Design Requirements

The TDP1204 can be designed into many different applications. In all the applications there are certain requirements for the system to work properly. The EN pin must have a 0.1-µF capacitor to ground. The processor can drive the EN pin, but the EN pin needs to change states (low to high) after the voltage rails have stabilized. Using I2C is the best way to configure the device, but pin strapping is also provided as I2C and is not available in all cases. As sources may have many different naming conventions, it is necessary to confirm that the link between the source and the TDP1204 are correctly mapped. A Swap function is provided for the input pins in case signaling is reversed between the source and receptacle. Table 9-1 lists information on expected values to perform properly.

For this design example, the TDP1204 is assumed to be configured for pin-strap mode. If I2C mode is desired, the MODE pin should be set to "F" and software must configure TDP1204. For how to configure TDP1204, refer to Section 8.4.1.

Table 9-1 Design Parameters
Design ParameterValue
VCC3.3-V
VIO (1.2-V, 1.8-V, or 3.3-V LVCMOS levels)1.8-V
Maximum HDMI 2.1 FRL Datarate (3, 6, 8, 10, or 12-Gbps)12-Gbps
Pin-strap or I2C mode (if I2C, then MODE = "F"). Pin-strap
Pin Strap Mode.(MODE = "0", "R" or "1").Mode = "0" (Fixed EQ with DDC Buffer support)
DDC Snoop Feature. (Y/N). Required when in pin strap. Optional in I2C mode.Yes
SWAP function (Y / N). In pin strap mode controlled by SDA/CFG1 pin.No. SDA/CFG1 pin = L.
DDC Level Shifter Support (Y / N)Yes
HPD_IN to HPD_OUT Level Shifter Support (Y / N)Yes, HPD_OUT is used. If no, then HPD_OUT can be left floating.
Pre-Channel Length (Table 9-2 provides the length restrictions)Length = 8 inches (≅ 7.2-dB at 6-GHz insertion loss)
Post-Channel Length (Table 9-2 provides the length restrictions)Length = 2 inches (≅ 1.8-dB at 6-GHz insertion loss)
Limited or linear redriver mode?Limited redriver (LINEAR_EN pin = "0").
TX is DC or AC-coupled to HDMI receptacle? DC-coupled. AC_EN pin = Low.
GPU Launch Voltage (500 mV to 1200 mV) if using limited redriver mode. If using linear redriver mode, then refer to the GPU requirements listed in Table 8-4.500-mV
GPU HDMI 2.1 pre-shoot and de-emphasis levels used if using redriver in limited modeIf MODE = "0" or "R", GPU's TX FFE pre-shoot and de-emphasis levels shall be set to 0-dB for all four TXFFE levels
If MODE = "1", then GPU TXFFE pre-shoot and de-emphasis levels shall meet the requirements listed in Table 8-4.
CTLE HDMI Datarate Map (Map A, Map B, or Map C) Map C
RX EQ (16 possible values. Value chosen based on pre-channel length).EQ1 pin: "R"
ADDR/EQ0 pin: "R"(7.5-dB)
TX Pre-emphasis. In pre-strap mode controlled by TXPRE pin.Default 0-dB of pre-emphasis. Float TXPRE pin.
TX Swing. In pre-strap mode controlled by TXSWG pin.Default TX swing level. Float TXSWG pin.
Table 9-2 Source Layout and Component Placement Constraints
Symbol Parameter Condition Min Typ Max Units
RESD External series resistor between ESD component and TDP1204 0 2.5 Ω
LAB(1)(3) PCB trace length from GPU to TDP1204 At 12-Gbps 1 10 inches
LINTRA-AB Intra-pair skew from GPU to TDP1204 5 mil
LCD(1) PCB trace length from TDP1204 to receptacle At 12-Gbps 0.75 2 inches
LINTRA-CD Intra-pair skew from TDP1204 to receptacle 5 mil
LCAP-RX PCB trace length from TDP1204 to optional external CAC-RX capacitor 0.3 inches
LCAP-TX PCB trace length from TDP1204 to optional external CAC-TX capacitor 0.3 inches
LESD PCB trace length from ESD component to receptacle 0.5 inches
LR_ESD PCB trace length from RESD to ESD component 0.25 inches
LINTER-PAIR(3) Inter-pair skew between all four channels (D0, D1, D2, and CLK) 1 inches
ILPCB PCB trace insertion loss 0.1 0.17 dB / inch / GHz
ZPCB_AB Differential impedance of LAB 75 110 Ω
ZPCB_CD Differential impedance of LCD 90 110 Ω
VIAAB Number of vias between GPU and TDP1204 2 VIA
VIACD Number of vias between HDMI connector and TDP1204 1 VIA
XTALK Differential crosstalk between adjacent differential pairs on PCB. ≦ 3 GHz −24 dB
(1) Maximum distance assumes PCB trace insertion loss meets ILPCB requirement. If PCB trace insertion loss exceeds the maximum limit, then distance needs be reduced.
(3) Minimum distance assumes PCB trace insertion loss meets ILPCB requirement. If PCB trace insertion loss is less than the minimum limit, then distance needs to be increased.
(3) Calculation of channel length is the sum of LAB and LCD.