JAJSO82 January   2024 THVD9491-SEP

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings [IEC]
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Power Dissipation
    7. 5.7 Electrical Characteristics
    8. 5.8 Switching Characteristics: 20Mbps
    9. 5.9 Switching Characteristics: 50Mbps
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 ±70-V Fault Protection
      2. 7.3.2 Integrated IEC ESD and EFT Protection
      3. 7.3.3 Driver Overvoltage and Overcurrent Protection
      4. 7.3.4 Enhanced Receiver Noise Immunity
      5. 7.3.5 Receiver Fail-Safe Operation
      6. 7.3.6 Low-Power Shutdown Mode
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Transient Protection
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Robust and reliable bus node design often requires the use of external transient protection devices to protect against surge transients that may occur in industrial environments. Since these transients have a wide frequency bandwidth (from approximately 3MHz to 300MHz), high-frequency layout techniques should be applied during PCB design.

  1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across the board.
  2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the path of least impedance and not the path of least resistance.
  3. Design the protection components into the direction of the signal path. Do not force the transient currents to divert from the signal path to reach the protection device.
  4. Apply 100nF to 220nF decoupling capacitors as close as possible to the VCC/VIO pins of transceiver, UART and/or controller ICs on the board.
  5. Use at least two vias for VCC/VIO and ground connections of decoupling capacitors and protection devices to minimize effective via inductance.
  6. Use 1kΩ to 10kΩ pull-up and pull-down resistors for enable lines to limit noise currents in these lines during transient events.
  7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.