JAJSI95 December   2019 TL16C750E

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. 7.1      ESD Ratings
    3. Table 2. Recommended Operating Conditions
    4. Table 3. Thermal Information
    5. Table 4. Electrical Characteristics
    6. Table 5. Timing Requirements
    7. 7.2      Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  UART Modes
      2. 9.3.2  Trigger Levels
      3. 9.3.3  Hardware Flow Control
      4. 9.3.4  Auto-RTS
      5. 9.3.5  Auto-CTS
      6. 9.3.6  Software Flow Control
      7. 9.3.7  Software Flow Control Example
      8. 9.3.8  Reset
      9. 9.3.9  Interrupts
      10. 9.3.10 Interrupt Mode Operation
      11. 9.3.11 Polled Mode Operation
      12. 9.3.12 Break and Timeout Conditions
      13. 9.3.13 Programmable Baud Rate Generator with Fractional Divisor
      14. 9.3.14 Fractional Divisor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Interface Mode
        1. 9.4.1.1 IOR Used (MODE = VCC)
        2. 9.4.1.2 IOR Unused (MODE = GND)
      2. 9.4.2 DMA Signaling
        1. 9.4.2.1 Single DMA Transfers (DMA Mode 0 or FIFO Disable)
        2. 9.4.2.2 Block DMA Transfers (DMA Mode 1)
      3. 9.4.3 Sleep Mode
    5. 9.5 Register Maps
      1. 9.5.1  Registers Operations
      2. 9.5.2  Receiver Holding Register (RHR)
      3. 9.5.3  Transmit Holding Register (THR)
      4. 9.5.4  FIFO Control Register (FCR)
      5. 9.5.5  Line Control Register (LCR)
      6. 9.5.6  Line Status Register (LSR)
      7. 9.5.7  Modem Control Register (MCR)
      8. 9.5.8  Modem Status Register (MSR)
      9. 9.5.9  Interrupt Enable Register (IER)
      10. 9.5.10 Interrupt Identification Register (IIR)
      11. 9.5.11 Enhanced Feature Register (EFR)
      12. 9.5.12 Divisor Latches (DLL, DLH, DLF)
      13. 9.5.13 Transmission Control Register (TCR)
      14. 9.5.14 Trigger Level Register (TLR)
      15. 9.5.15 FIFO Ready Register
      16. 9.5.16 Alternate Function Register (AFR)
      17. 9.5.17 RS-485 Mode
      18. 9.5.18 IrDA Overview
      19. 9.5.19 IrDA Encoder Function
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Set the desired baud rate
        2. 10.2.2.2 Reset the fifos
        3. 10.2.2.3 Sending data on the bus
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.13 Programmable Baud Rate Generator with Fractional Divisor

The TL16C750E UART contains a programmable baud generator that divides reference clock by a divisor in the range between 1 and (216 − 1) and a decimal resolution of 1/64. The output frequency of the baud rate generator is 8× or 16× the baud rate, depending on the value of DLF[7]. An additional divide-by-4 prescaler is also available and can be selected by MCR[7] as shown in the following. The formula for the divisor is:

Where 'baud divider' is either 8 or 16, depending on the value of DLF[7]. By default, DLF[7] = 0, which corresponds to a baud divider of 16 and
TL16C750E sllsf10_prescaler_text.gif

Figure 26 shows the internal prescaler and baud rate generator circuitry.

TL16C750E sllsf10_prescaler.gifFigure 26. Prescaler and Baud Rate Generator Block Diagram

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both 0, the UART is effectively disabled, because no baud clock is generated. The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 10 and Table 11 show the baud rate and divisor correlation for the crystal with frequency 1.8432 and 3.072 MHz, respectively.

Table 10. Baud Rates Using a 1.8432-MHz Crystal

DESIRED BAUD RATE DIVISOR USED TO GENERATE 16× CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL
50 2304 0
75 1536 0
110 1047 0.026
134.5 857 0.058
150 768 0
300 384 0
600 192 0
1200 96 0
1800 64 0
2000 58 0.69
2400 48 0
3600 32 0
4800 24 0
7200 16 0
9600 12 0
19200 6 0
38400 3 0
56000 2 2.86

Table 11. Baud Rates Using a 3.072-MHz Crystal

DESIRED BAUD RATE DIVISOR USED TO GENERATE 16× CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL
50 3840 0
75 2560 0
110 1745 0.026
134.5 1428 0.034
150 1280 0
300 640 0
600 320 0
1200 160 0
1800 107 0.312
2000 96 0
2400 80 0
3600 53 0.628
4800 40 0
7200 27 1.23
9600 20 0
19200 10 0
38400 5 0

Figure 27 shows the crystal clock circuit reference.

TL16C750E typxtalclk_sllset4.gif
A. For crystal with fundamental frequency from 1 to 24 MHz
B. For input clock frequency higher than 24 MHz, the crystal is not allowed and the oscillator must be used, because the TL16C750E internal oscillator cell can only support the crystal frequency up to 24 MHz.
Figure 27. Typical Crystal Clock Circuits