SLVSA79A April   2010  – September 2016 TL1963A-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable Operation
      2. 7.3.2 Output Capacitance and Transient Response
      3. 7.3.3 Overload Recovery
      4. 7.3.4 Output Voltage Noise
      5. 7.3.5 Protection Features
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Capacitance and Transient Response
    2. 8.2 Typical Application
      1. 8.2.1 Adjustable Output Operation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Fixed Operation
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Paralleling Regulators for Higher Output Current
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Calculating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

This section highlights some of the design considerations when implementing this device in various applications.

8.1.1 Output Capacitance and Transient Response

The TL1963A-Q1 regulators are designed to be stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. A minimum output capacitor of 10 µF with an ESR of 3 Ω or less is recommended to prevent oscillations. Larger values of output capacitance can decrease the peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the TL1963A-Q1, increase the effective output capacitor value.

Carefully consider the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. The most common dielectrics used are Z5U, Y5V, X5R, and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but exhibit strong voltage and temperature coefficients. When used with a 5-V regulator, a 10-µF Y5V capacitor can exhibit an effective value as low as 1 µF to 2 µF over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values.

Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients.

8.2 Typical Application

8.2.1 Adjustable Output Operation

TL1963A-Q1 adjovo_slvsa79a.gif
All capacitors are ceramic
Figure 30. Adjustable Output Voltage Schematic

8.2.1.1 Design Requirements

Table 2 lists the design requirements for this application example.

Table 2. Example Parameters

PARAMETER VALUE
Input voltage (VIN) 5 V
Output voltage (VOUT) 2.5 V
Output current (IOUT) 0 A to 1 A
Load regulation 1%

8.2.1.2 Detailed Design Procedure

The TL1963A-Q1 has an adjustable output voltage range of 1.21 V to 20 V. The output voltage is set by the ratio of two external resistors R1 and R2 as shown in Figure 30. The device maintains the voltage at the ADJ pin at 1.21 V referenced to ground. The current in R1 is then equal to (1.21 V/R1), and the current in R2 is the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, 3 µA at 25°C, flows through R2 into the ADJ pin. The output voltage can be calculated using Equation 2.

Equation 2. TL1963A-Q1 equation_01_slvsa79a.gif

The value of R1 must be less than 4.17 kΩ to minimize errors in the output voltage caused by the ADJ pin bias current. Note that in shutdown the output is turned off, and the divider current is zero. For an output voltage of 2.5 V, R1 is set to 4 kΩ. R2 is then found to be 4.22 kΩ using the equation above in Equation 3.

Equation 3. TL1963A-Q1 equation_02_slvsa79a.gif

where

  • VOUT = 2.5 V

The adjustable device is tested and specified with the ADJ pin tied to the OUT pin for an output voltage of 1.21 V. Specifications for output voltages greater than 1.21 V are proportional to the ratio of the desired output voltage to 1.21 V = VOUT/1.21 V. For example, load regulation for an output current change of 1 mA to 1.5 A is –2 mV (typical) at VOUT = 1.21 V. At VOUT = 2.5 V, the typical load regulation is calculated with Equation 4.

Equation 4. TL1963A-Q1 equation_03_slvsa79a.gif

Figure 33 shows the actual change in output is approximately 3 mV for a 1-A load step. The maximum load regulation at 25°C is –8 mV. At VOUT = 2.5 V, the maximum load regulation is calculated with Equation 5.

Equation 5. TL1963A-Q1 equation_04_slvsa79a.gif

Because 16.53 mV is only 0.7% of the 2.5-V output voltage, the load regulation meets the design requirements.

8.2.1.2.1 Fixed Operation

The TL1963A-Q1 can be used in a fixed voltage configuration. The SENSE/ADJ pin must be connected to OUT for proper operation. An example of this is shown in Figure 31. The TL1963A-Q1 can also be used in this configuration for a fixed output voltage of 2.5 V.

TL1963A-Q1 app_33_25_slvsa79a.gif Figure 31. 3.3-V to 2.5-V Regulator

During fixed voltage operation, the SENSE/ADJ pin can be used for a Kelvin connection if routed separately to the load (see Figure 32). This allows the regulator to compensate for voltage drop across parasitic resistances (RP) between the output and the load. This becomes more crucial with higher load currents.

TL1963A-Q1 app_kelvin_slvsa79a.gif Figure 32. Kelvin Sense Connection

8.2.1.3 Application Curve

TL1963A-Q1 SLVSA79_load_trans_curve.png Figure 33. 1-A Load Transient Response (COUT = 10 µF)

8.2.2 Paralleling Regulators for Higher Output Current

TL1963A-Q1 app_parallel_slvsa79a.gif
All capacitors are ceramic
Figure 34. Paralleling Regulator Schematic

8.2.2.1 Design Requirements

Table 3 lists the design requirements for this application example.

Table 3. Example Parameters

PARAMETER VALUE
Input voltage (VIN) 6 V
Output voltage (VOUT) 3.3 V
Output current (IOUT) 3 A

8.2.2.2 Detailed Design Procedure

In an application requiring higher output current, an adjustable output regular can be placed in parallel with a fixed output regulator to increase the current capacity. Two sense resistors and a comparator can be used to control the feedback loop of the adjustable regulator to balance the current between the two regulators.

In Figure 34, resistors R1 and R2 are used to sense the current flowing into each regulator and must have a very low resistance to avoid unnecessary power loss. R1 and R2 must have the same value and a tolerance of 1% or better so the current is shared equally between the regulators. For this example, a value of 0.01 Ω is used.

The TLV3691 rail-to-rail nanopower comparator output alternates between VIN and GND depending on the currents flowing into each of the two regulators. To design this control circuit, begin by looking at the case where the two output currents are approximately equal and the comparator output is low. In this case, the output of the TL1963A-Q1 must be set the same as the fixed voltage regulator. The TL1963A-Q1-3.3 has a 3.3-V fixed output, so this is the set point for the adjustable regulator. Begin by selecting a R7 value less than 4.17 kΩ. In this example, 3.3 kΩ is used. R5 requires a high resistance to satisfy Equation 9, for this example 100-kΩ is chosen. Then find the parallel resistance of R5 and R7 because they are both connected from the ADJ pin to GND using Equation 6.

Equation 6. TL1963A-Q1 equation_05_slvsa79a.gif

Once the R5 and R7 parallel resistance in calculated, the value for R6 are found using Equation 7.

Equation 7. TL1963A-Q1 equation_06_slvsa79a.gif
Equation 8. TL1963A-Q1 equation_07_slvsa79a.gif

where

  • R6 = 5.45 kΩ

In the case where the TL1963A-Q1-3.3 is sourcing more current than TL1963A-Q1, the comparator output goes high.

This lowers the voltage at the ADJ pin causing the TL1963A-Q1 to try and raise the output voltage by sourcing more current. The TL1963A-Q1-3.3 then reacts by sourcing less current to try and keep the output from rising.

When the current through the TL1963A-Q1-3.3 becomes less than the TL1963A-Q1, the comparator output returns to GND. In order for this to happen, Equation 9 must be satisfied.

Equation 9. TL1963A-Q1 equation_08_slvsa79a.gif
Equation 10. TL1963A-Q1 equation_09_slvsa79a.gif

where

  • 0.33 V < 1.21 V

8.2.2.3 Application Curve

TL1963A-Q1 SLVSA79_parallel_reg_curve.png Figure 35. Parallel Regulators Sharing Load Current