SLDS156B March 2009 – July 2015 TLC59108
PRODUCTION DATA.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | 0 | 7 | V | |
VI | Input voltage | –0.4 | 7 | V | |
VO | Output voltage | –0.5 | 20 | V | |
IO | Output current | 120 | mA | ||
TJ | Junction temperature | –40 | 150 | °C | |
Tstg | Storage temperature | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) | ±1000 |
(1) | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | 3 | 5.5 | V | ||
VIH | High-level input voltage | SCL, SDA, RESET, A0, A1, A2, A3 | 0.7 × VCC | VCC | V | |
VIL | Low-level input voltage | SCL, SDA, RESET, A0, A1, A2, A3 | 0 | 0.3 × VCC | V | |
VO | Supply voltage to output pins | OUT0 to OUT7 | 17 | V | ||
IOL | Low-level output current sink | SDA | VCC = 3 V | 20 | mA | |
VCC = 3 V | 30 | |||||
IO | Output current | OUT0 to OUT7 | 5 | 120 | mA | |
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC (1) | TLC59108 | UNIT | ||
---|---|---|---|---|
PW (TSSOP) | RGY (VQFN) | |||
20 PINS | 20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 98.9 | 39.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 32.9 | 44.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 49.9 | 14.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.7 | 1.0 | °C/W |
ψJB | Junction-to-board characterization parameter | 49.3 | 14.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | – | 7.6 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP (1) | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
II | Input/output leakage current | SCL, SDA, A0, A1, A2, A3, RESET | VI = VCC or GND | ±0.3 | μA | |||
Output leakage current | OUT0 to OUT7 | VO = 17 V, TJ = 25°C | 0.5 | μA | ||||
VPOR | Power-on reset voltage | 2.5 | V | |||||
IOL | Low-level output current | SDA | VCC = 3 V, VOL = 0.4 V | 20 | mA | |||
VCC = 5 V, VOL = 0.4 V | 30 | |||||||
IO(1) | Output current 1 | OUT0 to OUT7 | VO = 0.6 V, Rext = 720 Ω, CG = 0.992 | 26 | mA | |||
Output current error | OUT0 to OUT7 | IO = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C | ±8% | |||||
Output channel to channel current error | OUT0 to OUT7 | IO = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C | ±3% | |||||
IO(2) | Output current 2 | OUT0 to OUT7 | VO = 0.8 V, Rext = 360 Ω, CG = 0.992 | 52 | mA | |||
Output current error | OUT0 to OUT7 | IO = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C | ±8% | |||||
Output channel to channel current error | OUT0 to OUT7 | IO = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C | ±3% | |||||
IOUT vs VOUT | Output current vs output voltage regulation | OUT0 to OUT7 | VO = 1 V to 3 V, IO = 26 mA | ±0.1 | %/V | |||
VO = 3 V to 5.5 V, IO = 26 mA to 120 mA | ±1 | |||||||
IOUT,Th1 | Threshold current 1 for error detection | OUT0 to OUT7 | IOUT,target = 26 mA | 0.5% × ITARGET | ||||
IOUT,Th2 | Threshold current 2 for error detection | OUT0 to OUT7 | IOUT,target = 52 mA | 0.5% × ITARGET | ||||
IOUT,Th3 | Threshold current 3 for error detection | OUT0 to OUT7 | IOUT,target = 104 mA | 0.5% × ITARGET | ||||
TSD | Overtemperature shutdown (2) | 150 | 175 | 200 | °C | |||
THYS | Restart hysteresis | 15 | °C | |||||
Ci | Input capacitance | SCL, A0, A1, A2, A3, RESET | VI = VCC or GND | 5 | pF | |||
Cio | Input/output capacitance | SDA | VI = VCC or GND | 5 | pF | |||
ICC | Supply current | VCC = 5.5 V | OUT0 to OUT7 = OFF, Rext = Open | 17 | mA | |||
OUT0 to OUT7 = OFF, Rext = 720 Ω | 20 | |||||||
OUT0 to OUT7 = OFF, Rext = 360 Ω | 23 | |||||||
OUT0 to OUT7 = OFF, Rext = 180 Ω | 28 | |||||||
OUT0 to OUT7 = ON, Rext = 720 Ω | 21 | |||||||
OUT0 to OUT7 = ON, Rext = 360 Ω | 23 | |||||||
OUT0 to OUT7 = ON, Rext = 180 Ω | 28 |
STANDARD MODE I2C BUS |
FAST MODE I2C BUS |
FAST MODE PLUS I2C BUS |
UNIT | |||||
---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||
I2C Interface | ||||||||
fSCL | SCL clock frequency | 0 | 100 | 0 | 400 | 0 | 1000 | kHz |
tBUF | I2C bus free time between stop and start | 4.7 | 1.3 | 0.5 | μs | |||
tHD;STA | Hold time (repeated) Start condition | 4 | 0.6 | 0.26 | μs | |||
tSU;STA | Set-up time for a repeated Start condition | 4.7 | 0.6 | 0.26 | μs | |||
tSU;STO | Set-up time for Stop condition | 4 | 0.6 | 0.26 | μs | |||
tHD;DAT | Data hold time | 0 | 0 | 0 | ns | |||
tVD;ACK | Data valid acknowledge time (1) | 0.3 | 3.45 | 0.1 | 0.9 | 0.05 | 0.45 | μs |
tVD;DAT | Data valid time (2) | 0.3 | 3.45 | 0.1 | 0.9 | 0.05 | 0.45 | μs |
tSU;DAT | Data set-up time | 250 | 100 | 50 | ns | |||
tLOW | Low period of the SCL clock | 4.7 | 1.3 | 0.5 | μs | |||
tHIGH | High period of the SCL clock | 4 | 0.6 | 0.26 | μs | |||
tf | Fall time of both SDA and SCL signals (4)(5) | 300 | 20+0.1Cb(3) | 300 | 120 | ns | ||
tr | Rise time of both SDA and SCL signals | 1000 | 20+0.1Cb(3) | 300 | 120 | ns | ||
tSP | Pulse width of spikes that must be suppressed by the input filter (6) | 50 | 50 | 50 | ns | |||
Reset | ||||||||
tW | Reset pulse width | 10 | 10 | 10 | ns | |||
tREC | Reset recovery time | 0 | 0 | 0 | ns | |||
tRESET | Time to reset (7)(8) | 400 | 400 | 400 | ns |