JAJSFP3A July   2018  – August 2018 TLC6C5716-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Constant-Sink-Current Setting
      2. 7.3.2 Brightness Control and Dot Correction
      3. 7.3.3 Grayscale Configuration
        1. 7.3.3.1 PWM Auto Repeat
        2. 7.3.3.2 PWM Timing Reset
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  LED Diagnostics
        2. 7.3.4.2  Adjacent-Pin-Short Check
        3. 7.3.4.3  IREF-Short and IREF-Open Detection
        4. 7.3.4.4  Pre-Thermal Warning Flag
        5. 7.3.4.5  Thermal Error Flag
        6. 7.3.4.6  Negate-Bit Toggle
        7. 7.3.4.7  LOD_LSD Self-Test
        8. 7.3.4.8  ERR Pin
        9. 7.3.4.9  ERROR Clear
        10. 7.3.4.10 Global Reset
        11. 7.3.4.11 Slew Rate Control
        12. 7.3.4.12 Channel Group Delay
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up
      2. 7.4.2 Device Initialization
      3. 7.4.3 Fault Mode
      4. 7.4.4 Normal Operation
    5. 7.5 Programming
      1. 7.5.1 Register Write and Read
        1. 7.5.1.1 FC-BC-DC Write
          1. 7.5.1.1.1 FC Data Write
          2. 7.5.1.1.2 BC Data Write
          3. 7.5.1.1.3 DC Data Write
        2. 7.5.1.2 Grayscale Data Write
        3. 7.5.1.3 Special Command Function
          1. 7.5.1.3.1 GS Read
          2. 7.5.1.3.2 FC-BC-DC Read
          3. 7.5.1.3.3 Status Information Data Read
    6. 7.6 Register Maps
      1. 7.6.1 GRAYSCALE Registers
        1. 7.6.1.1 OUTn_GS Register (Offset = 0h)
          1. Table 25. OUTn_GS Register Field Descriptions
      2. 7.6.2 FC-BC-DC Registers
        1. 7.6.2.1 FC-BC-DC Register (Offset = 1h)
          1. Table 28. FC-BC-DC Register Field Descriptions
      3. 7.6.3 SID Registers
        1. 7.6.3.1 SID Register (Offset = 2h)
          1. Table 31. SID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VCC = 3 V to 5.5 V, TJ=–40°Cto150°C,VSENSE = 5 V, GS = FFFh, BC = FFh, DC = 7Fh with upper dotcorrection(DC)range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VCC, GND)
ICC Supply current SDI, SCK, LATCH = L, BLANK = L, GCLK = L, VOUT = 1 V, IOUT = 2 mA 4.2 5.5 mA
SDI, SCK, LATCH = L, BLANK = L, GCLK = L, VOUT = 1 V, IOUT = 20 mA 7.7 9
SDI, SCK, LATCH = L, BLANK = H, GCLK = 8 MHz, VOUT = 1 V, IOUT = 20 mA , auto-repeat on 8.3 10
SDI, SCK, LATCH = L, BLANK = H, GCLK = 8 MHz, VOUT = 1 V, IOUT = 50 mA , auto-repeat on 13.5 16
LOGIC INPUTS (SDI, SCK, LATCH, GCLK, BLANK)
IIkg Input leakage current VI at SCK, LATCH, GCLK = VCC; VI at SDI, SCK, LATCH, BLANK, GCLK = GND –1 1 µA
Rpd Pulldown resistance at BLANK, GCLK 250 500 750 kΩ
CONTROL OUTPUTS (IREF, ERR, SDO)
VIREF IREF voltage RIREF = 0.96 kΩ 1.17 1.2 1.23 V
VOH High-level output voltage At SDO, IOH = –1 mA VCC – 0.4 VCC V
VOL Low-level output voltage At SDO, IOL = 1 mA 0.4 V
VERR ERR pin open-drain voltage drop IERR = 4 mA 0.1 VCC V
Ilkg(ERR) ERR pin leakage current VERR = 5 V 1 µA
OUTPUT STAGE
V(OUT,min) Minimum output voltage VCC = 3.6 V, IOUT = 50 mA 0.67 V
VCC = 3 V, IOUT = 50 mA 0.7
K(OUT) Ratio of output current to IREF current, K = I(OUTx) / I(IREF) 40 mA/mA
Ilkg(OUT) Output leakage current BLANK = L, VOUT = 7 V, VSENSE = 7 V, IOUT = 50 mA 0.1 µA
CHANNEL ACCURACY
I(OUT) Constant output current VOUT = 1 V, RIREF = 24 kΩ 1.86 2 2.14 mA
VOUT = 1 V, RIREF = 0.96 kΩ 46.5 50 53.5
VOUT = 1V, RIREF open or short 7 10 13
ΔI(Ch-Ch)(1) Current accuracy (channel-to-channel in same color group) VOUT = 1 V, IOUT = 50 mA –4% 4%
VOUT = 1 V, IOUT = 2 mA –4% 4%
ΔI(Dev-Dev)(2) Current accuracy (device-to-device) VOUT= 1 V, IOUT = 50 mA –4% 4%
VOUT = 1 V, IOUT = 2 mA –4% 4%
ΔI(Ch-Ideal)(3) Current accuracy (channel-to-ideal output) VOUT = 1 V, IOUT = 50 mA –7% 7%
VOUT = 1 V, IOUT = 2 mA –7% 7%
ΔI(OUT-VCC)(4) Line regulation VOUT = 1 V, IOUT = 50 mA –0.7 0.7 %/V
VOUT = 1 V, IOUT = 2 mA –0.7 0.7
ΔI(OUT-VOUT)(5) Load regulation VOUT = 1 V to 3 V, IOUT = 50 mA –0.7 0.7
VOUT = 1 V to 3 V, IOUT = 2 mA –0.7 0.7
PROTECTION CIRCUITS
VLOD LED open-circuit detection threshold LOD_VOLTAGE = 0b 0.275 0.3 0.32 V
LOD_VOLTAGE = 1b 0.48 0.5 0.52
VLSD LED short-circuit detection threshold LSD_VOLTAGE = 0b VSENSE – 0.4 VSENSE – 0.3 VSENSE – 0.2 V
LSD_VOLTAGE = 1b VSENSE – 0.8 VSENSE – 0.7 VSENSE – 0.6
IIREF_OC IREF resistor open-circuit detection threshold VCC = 5 V 8 10 12 µA
IIREF_OCHYS IREF resistor open-circuit detection threshold hysteresis VCC = 5 V 5 µA
IIREF_SC IREF resistor short-circuit-detection threshold VCC = 5 V 2 2.7 3.2 mA
IIREF_SCHYS IREF resistor short-circuit-detection threshold hysteresis VCC = 5 V 0.3 mA
TPTW Pre-thermal warning flag threshold 125 135 145 °C
THYS_PTW Pre-thermal warning flag hysteresis 10 °C
TSD Thermal error flag threshold 150 160 170 °C
THYS_TEF Thermal error flag hysteresis 10 °C
(1) Channel to channel accuracy in the same color group iscalculated by the formula below. (X = color group; i,j = 0 to 7 )
TLC6C5716-Q1 CH-CH-Accuracy-5716.gif
(2) Device to device accuracy is calculated by the formulabelow.
TLC6C5716-Q1 Dev-Dev-Accuracy-5716.gif
TLC6C5716-Q1 Ideal-Output-Current-5716.gif
(3) Channel to ideal accuracy is calculated by the formulabelow.
TLC6C5716-Q1 CH-Ideal-Accuracy-5716.gif
(4) Line regulation accuracy is calculated by the formulabelow.
TLC6C5716-Q1 Line-Regulation-5716.gif
(5) Load regulation accuracy is calculated by the formulabelow.
TLC6C5716-Q1 Load-Regulation-5716.gif