JAJSGP7B May   2012  – December 2018 TLV320DAC3203

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, Bypass Outputs
    6. 6.6  Electrical Characteristics, Microphone Interface
    7. 6.7  Electrical Characteristics, Audio Outputs
    8. 6.8  Electrical Characteristics, LDO
    9. 6.9  Electrical Characteristics, Misc.
    10. 6.10 Electrical Characteristics, Logic Levels
    11. 6.11 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
    12. 6.12 Typical DSP Timing Characteristics
    13. 6.13 I2C Interface Timing
    14. 6.14 SPI Interface Timing (See )
    15. 6.15 Typical Characteristics
      1. 6.15.1 Typical Characteristics, FFT
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Connections
        1. 7.3.1.1 Digital Pins
          1. 7.3.1.1.1 Multifunction Pins
        2. 7.3.1.2 Analog Pins
      2. 7.3.2 Analog Audio I/O
        1. 7.3.2.1 Analog Low Power Bypass
        2. 7.3.2.2 Headphone Outputs
      3. 7.3.3 Digital Microphone Inteface
        1. 7.3.3.1 ADC Processing Blocks — Overview
          1. 7.3.3.1.1 Processing Blocks
      4. 7.3.4 DAC
        1. 7.3.4.1 DAC Processing Blocks — Overview
      5. 7.3.5 Powertune
      6. 7.3.6 Digital Audio I/O Interface
      7. 7.3.7 Clock Generation and PLL
      8. 7.3.8 Control Interfaces
        1. 7.3.8.1 I2C Control
        2. 7.3.8.2 SPI Control
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3.1.1 Processing Blocks

The TLV320DAC3203 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied.

Table 2 gives an overview of the available processing blocks and their properties.

The signal processing blocks available are:

  • First-order IIR
  • Scalable number of biquad filters
  • Variable-tap FIR filter

The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column (RC) gives an approximate indication of power consumption.

Table 2. Processing Blocks

Processing Blocks Channel Decimation
Filter		 1st Order
IIR Available		 Number
BiQuads		 FIR Required AOSR Value Resource
Class
PRB_R1(1) Stereo A Yes 0 No 128,64 6
PRB_R2 Stereo A Yes 5 No 128,64 8
PRB_R3 Stereo A Yes 0 25-Tap 128,64 8
PRB_R4 Right A Yes 0 No 128,64 3
PRB_R5 Right A Yes 5 No 128,64 4
PRB_R6 Right A Yes 0 25-Tap 128,64 4
PRB_R7 Stereo B Yes 0 No 64 3
PRB_R8 Stereo B Yes 3 No 64 4
PRB_R9 Stereo B Yes 0 20-Tap 64 4
PRB_R10 Right B Yes 0 No 64 2
PRB_R11 Right B Yes 3 No 64 2
PRB_R12 Right B Yes 0 20-Tap 64 2
PRB_R13 Stereo C Yes 0 No 32 3
PRB_R14 Stereo C Yes 5 No 32 4
PRB_R15 Stereo C Yes 0 25-Tap 32 4
PRB_R16 Right C Yes 0 No 32 2
PRB_R17 Right C Yes 5 No 32 2
PRB_R18 Right C Yes 0 25-Tap 32 2
(1) Default

For more detailed information see the TLV320DAC3203 Application Reference Guide