JAJSPA8 September   2020 TLV4011-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Dissipation Ratings
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 SENSE Monitoring
      2. 7.3.2 Transient Immunity
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Undervoltage Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Additional Application Information
        1. 8.2.2.1 Pull-up Resistor Selection
        2. 8.2.2.2 Input Supply Capacitor
        3. 8.2.2.3 Sense Capacitor
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.2 Detailed Design Procedure

Configure the circuit as shown in Figure 8-1. Note that VDD of the comparator is connected directly to VBAT (the battery being monitored) and the output of the comparator is level shifted with its open-drain ouput to 3.3 V which powers the micro-controller. Resistors R1 and R2 divide down VBAT so that the resistor divided output equals 1.226 V when VBAT reaches an undervoltage alert level of 2.0 V.

When the battery voltage sags down to 2.0 V, the resistor divider voltage crosses the (VIT = 1.226 V) threshold of the TLV4011-Q1. This causes the comparator output to transition from a logic high to a logic low. An open-drainj comparator is selected so the comparator output is compatible with the input logic level of the microcontroller. In addition, selecting a comparator with an integrated reference value of 1.226 V is favorable because it is the closest internal reference option that is less than the critical undervoltage level of 2.0 V. Choosing the internal reference option that is closest to the critical undervoltage level minimizes the resistor divider ratio which optimizes the accuracy of the circuit. Error at the falling edge threshold of (VIT) is amplified by the inverse of the resistor divider ratio. So minimizing the resistor divider ratio is a way of optimizing voltage monitoring accuracy.

Equation 1 is derived from the analysis of Figure 8-1.

Equation 1. GUID-F6C512C9-BEF1-4E21-BB07-A250727397AC-low.gif

where

  • R1 and R2 are the resistor values for the resistor divider connected to SENSE
  • VBAT is the voltage source that is being monitored for an undervoltage condition.
  • VIT is the falling edge threshold where the comparator output changes state from high to low

Rearranging Equation 1 and solving for R1 yields Equation 2.

Equation 2. GUID-50992912-40AE-4F47-93A4-DF17ECBB288E-low.gif

For the specific undervoltage detection of 2.0 V using the TLV4011-Q1, the following results are calculated.

Equation 3. GUID-3F3FCCB1-1D46-4580-A825-AB587D8744D8-low.gif

where

  • R2 is set to 1 MΩ
  • VBAT is set to 2.0 V
  • VIT is set to1.226 V

Choose RTOTAL (R1 + R2) such that the current through the divider is at approximately 100 times higher than the input bias current (IBIAS). The resistors can have high values to minimize current consumption in the circuit without adding significant error to the resistive divider.