JAJSKJ9A December   2020  – March 2023 TLV766-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage
      3. 7.3.3 Foldback Current Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Output Pulldown
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Device Feedback Resistors
      2. 8.1.2 Recommended Capacitor Types
      3. 8.1.3 Input and Output Capacitor Requirements
      4. 8.1.4 Reverse Current
      5. 8.1.5 Feed-Forward Capacitor (CFF)
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transient Response
        2. 8.2.2.2 Choose Feedback Resistors
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.2 Choose Feedback Resistors

For this design example, VOUT is set to 3.3 V. The following equations set the feedback divider resistors for the desired output voltage:

Equation 11. VOUT = VFB × (1 + R1 / R2)
Equation 12. R1 + R2 ≤ VOUT / (IFB × 100)

For improved output accuracy, use Equation 12 and IFB = 50 nA as listed in the Electrical Characteristics table in the Specifications section to calculate the upper limit for series feedback resistance (R1 + R2 ≤ 660 kΩ).

The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 0.8 V, as listed in the Electrical Characteristics table). Use Equation 11 to determine the ratio of R1 / R2 = 3.125. Use this ratio and solve Equation 12 for R2. Now calculate the upper limit for R2 ≤ 160 kΩ. Select a standard value resistor for R2 = 160 kΩ.

Reference Equation 11 and solve for R1:

Equation 13. R1 = (VOUT / VFB – 1) × R2

From Equation 13, R1 = 500 kΩ can be determined. Select a standard value resistor for R1 = 499 kΩ. VOUT = 3.3 V (as determined by Equation 11).