JAJSOZ7A August   2022  – April 2024 TMDS1204

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD and Latch-Up Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1  4-Level Inputs
      2. 7.2.2  I/O Voltage Level Selection
      3. 7.2.3  HPD_OUT
      4. 7.2.4  Lane Control
      5. 7.2.5  Swap
      6. 7.2.6  Linear and Limited Redriver
      7. 7.2.7  Main Link Inputs
      8. 7.2.8  Receiver Equalizer
      9. 7.2.9  CTLE Bypass
      10. 7.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 7.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 7.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 7.2.12 Input Signal Detect
        1. 7.2.12.1 SIGDET_OUT Indicator
      13. 7.2.13 Main Link Outputs
        1. 7.2.13.1 Transmitter Bias
        2. 7.2.13.2 Transmitter Impedance Control
        3. 7.2.13.3 TX Slew Rate Control
        4. 7.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 7.2.13.5 TX Swing Control
        6. 7.2.13.6 Fan-out Buffer
      14. 7.2.14 HDMI DDC Capacitance
      15. 7.2.15 DisplayPort
    3. 7.3 Device Functional Modes
      1. 7.3.1 MODE Control
        1. 7.3.1.1 I2C Mode (MODE = "F")
        2. 7.3.1.2 Pin Strap Modes
          1. 7.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 7.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ)
          3. 7.3.1.2.3 Pin-Strap HDMI 2.1 Function (Mode = "1"): Flexible Rx EQ
          4. 7.3.1.2.4 Pin-Strap HDMI 2.1 Function (Mode = "R"): Flexible Rx EQ and Fan-Out Buffer
      2. 7.3.2 DDC Snoop Feature
        1. 7.3.2.1 HDMI Type
        2. 7.3.2.2 HDMI 2.1 FRL Snoop
      3. 7.3.3 Low Power States
    4. 7.4 Programming
      1. 7.4.1 Pseudocode Examples
        1. 7.4.1.1 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
        2. 7.4.1.2 Sink Example
      2. 7.4.2 TMDS1204 I2C Address Options
      3. 7.4.3 I2C Target Behavior
    5. 7.5 Register Maps
      1. 7.5.1 TMDS1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Source-Side Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pre-Channel (LAB)
        2. 8.2.2.2 Post-Channel (LCD)
        3. 8.2.2.3 Common Mode Choke
        4. 8.2.2.4 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Typical Sink-Side Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedures
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Supply Decoupling
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 関連資料
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2.1 HDMI Type

Table 7-20 lists the TMDS1204 monitors offsets 20h and 31h to determine HDMI type as either HDMI 1.4, HDMI 2.0, or HDMI 2.1 FRL.

Table 7-20 HDMI Type Selection
HDMI Type TMDS_CLK_RATIO
SCDCS Offset 20h[1]		 FRL_RATE
SCDCS Offset 31h[3:0]
HDMI 1.4 (TMDS x10) 0 0h
HDMI 2.0 (TMDS x40) 1 0h
HDMI 2.1 FRL X Not 0h
Note: TMDS1204 will default to HDMI 1.4 following a power-on reset or whenever it enters the power down state. Upon exiting standby, the TMDS1204 will hold data rate value (HDMI 1.4, 2.0, or 2.1) prior to entering the standby.