JAJSTJ4A June   2022  – March 2024 TMS570LC4357-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 GWT BGA Package Ball-Map (337 Terminal Grid Array)
    2. 5.2 Terminal Functions
      1. 5.2.1 GWT Package
        1. 5.2.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 5.2.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 5.2.1.3  RAM Trace Port (RTP)
        4. 5.2.1.4  Enhanced Capture Modules (eCAP)
        5. 5.2.1.5  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        6. 5.2.1.6  Enhanced Pulse-Width Modulator Modules (ePWM)
        7. 5.2.1.7  Data Modification Module (DMM)
        8. 5.2.1.8  General-Purpose Input / Output (GIO)
        9. 5.2.1.9  FlexRay Interface Controller (FlexRay)
        10. 5.2.1.10 Controller Area Network Controllers (DCAN)
        11. 5.2.1.11 Local Interconnect Network Interface Module (LIN)
        12. 5.2.1.12 Standard Serial Communication Interface (SCI)
        13. 5.2.1.13 Inter-Integrated Circuit Interface Module (I2C)
        14. 5.2.1.14 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        15. 5.2.1.15 Ethernet Controller
        16. 5.2.1.16 External Memory Interface (EMIF)
        17. 5.2.1.17 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)
        18. 5.2.1.18 System Module Interface
        19. 5.2.1.19 Clock Inputs and Outputs
        20. 5.2.1.20 Test and Debug Modules Interface
        21. 5.2.1.21 Flash Supply and Test Pads
        22. 5.2.1.22 Supply for Core Logic: 1.2-V Nominal
        23. 5.2.1.23 Supply for I/O Cells: 3.3-V Nominal
        24. 5.2.1.24 Ground Reference for All Supplies Except VCCAD
        25. 5.2.1.25 Other Supplies
      2. 5.2.2 Multiplexing
        1. 5.2.2.1 Output Multiplexing
          1. 5.2.2.1.1 Notes on Output Multiplexing
        2. 5.2.2.2 Input Multiplexing
          1. 5.2.2.2.1 Notes on Input Multiplexing
          2. 5.2.2.2.2 General Rules for Multiplexing Control Registers
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 6.6  Wait States Required - L2 Memories
    7. 6.7  Power Consumption Summary
    8. 6.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 6.9  Thermal Resistance Characteristics for the BGA Package (GWT)
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Output Buffer Drive Strengths
      2. 6.10.2 Input Timings
      3. 6.10.3 Output Timings
  8. 7 System Information and Electrical Specifications
    1. 7.1  Device Power Domains
    2. 7.2  Voltage Monitor Characteristics
      1. 7.2.1 Important Considerations
      2. 7.2.2 Voltage Monitor Operation
      3. 7.2.3 Supply Filtering
    3. 7.3  Power Sequencing and Power-On Reset
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down Sequence
      3. 7.3.3 Power-On Reset: nPORRST
        1. 7.3.3.1 nPORRST Electrical and Timing Requirements
    4. 7.4  Warm Reset (nRST)
      1. 7.4.1 Causes of Warm Reset
      2. 7.4.2 nRST Timing Requirements
    5. 7.5  Arm Cortex-R5F CPU Information
      1. 7.5.1 Summary of Arm Cortex-R5F CPU Features
      2. 7.5.2 Dual Core Implementation
      3.      73
      4. 7.5.3 Duplicate Clock Tree After GCLK
      5. 7.5.4 Arm Cortex-R5F CPU Compare Module (CCM) for Safety
        1. 7.5.4.1 Signal Compare Operating Modes
          1. 7.5.4.1.1 Active Compare Lockstep Mode
          2. 7.5.4.1.2 Self-Test Mode
          3. 7.5.4.1.3 Error Forcing Mode
          4. 7.5.4.1.4 Self-Test Error Forcing Mode
        2. 7.5.4.2 Bus Inactivity Monitor
        3. 7.5.4.3 CPU Registers Initialization
      6. 7.5.5 CPU Self-Test
        1. 7.5.5.1 Application Sequence for CPU Self-Test
        2. 7.5.5.2 CPU Self-Test Clock Configuration
        3. 7.5.5.3 CPU Self-Test Coverage
      7. 7.5.6 N2HET STC / LBIST Self-Test Coverage
    6. 7.6  Clocks
      1. 7.6.1 Clock Sources
        1. 7.6.1.1 Main Oscillator
          1. 7.6.1.1.1 Timing Requirements for Main Oscillator
        2. 7.6.1.2 Low-Power Oscillator
          1. 7.6.1.2.1 Features
          2.        94
          3. 7.6.1.2.2 LPO Electrical and Timing Specifications
        3. 7.6.1.3 Phase-Locked Loop (PLL) Clock Modules
          1. 7.6.1.3.1 Block Diagram
          2. 7.6.1.3.2 PLL Timing Specifications
        4. 7.6.1.4 External Clock Inputs
      2. 7.6.2 Clock Domains
        1. 7.6.2.1 Clock Domain Descriptions
        2. 7.6.2.2 Mapping of Clock Domains to Device Modules
      3. 7.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      4. 7.6.4 Clock Test Mode
    7. 7.7  Clock Monitoring
      1. 7.7.1 Clock Monitor Timings
      2. 7.7.2 External Clock (ECLK) Output Functionality
      3. 7.7.3 Dual Clock Comparators
        1. 7.7.3.1 Features
        2. 7.7.3.2 Mapping of DCC Clock Source Inputs
    8. 7.8  Glitch Filters
    9. 7.9  Device Memory Map
      1. 7.9.1 Memory Map Diagram
      2. 7.9.2 Memory Map Table
      3. 7.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 7.9.4 Master/Slave Access Privileges
        1. 7.9.4.1 Special Notes on Accesses to Certain Slaves
      5. 7.9.5 MasterID to PCRx
      6. 7.9.6 CPU Interconnect Subsystem SDC MMR Port
      7. 7.9.7 Parameter Overlay Module (POM) Considerations
    10. 7.10 Flash Memory
      1. 7.10.1 Flash Memory Configuration
      2. 7.10.2 Main Features of Flash Module
      3. 7.10.3 ECC Protection for Flash Accesses
      4. 7.10.4 Flash Access Speeds
      5. 7.10.5 Flash Program and Erase Timings
        1. 7.10.5.1 Flash Program and Erase Timings for Program Flash
        2. 7.10.5.2 Flash Program and Erase Timings for Data Flash
    11. 7.11 L2RAMW (Level 2 RAM Interface Module)
      1. 7.11.1 L2 SRAM Initialization
    12. 7.12 ECC / Parity Protection for Accesses to Peripheral RAMs
    13. 7.13 On-Chip SRAM Initialization and Testing
      1. 7.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 7.13.1.1 Features
        2. 7.13.1.2 PBIST RAM Groups
      2. 7.13.2 On-Chip SRAM Auto Initialization
    14. 7.14 External Memory Interface (EMIF)
      1. 7.14.1 Features
      2. 7.14.2 Electrical and Timing Specifications
        1. 7.14.2.1 Read Timing (Asynchronous RAM)
        2. 7.14.2.2 Write Timing (Asynchronous RAM)
        3. 7.14.2.3 EMIF Asynchronous Memory Timing
        4. 7.14.2.4 Read Timing (Synchronous RAM)
        5. 7.14.2.5 Write Timing (Synchronous RAM)
        6. 7.14.2.6 EMIF Synchronous Memory Timing
    15. 7.15 Vectored Interrupt Manager
      1. 7.15.1 VIM Features
      2. 7.15.2 Interrupt Generation
      3. 7.15.3 Interrupt Request Assignments
    16. 7.16 ECC Error Event Monitoring and Profiling
      1. 7.16.1 EPC Module Operation
        1. 7.16.1.1 Correctable Error Handling
        2. 7.16.1.2 Uncorrectable Error Handling
    17. 7.17 DMA Controller
      1. 7.17.1 DMA Features
      2. 7.17.2 DMA Transfer Port Assignment
      3. 7.17.3 Default DMA Request Map
      4. 7.17.4 Using a GIO terminal as a DMA Request Input
    18. 7.18 Real-Time Interrupt Module
      1. 7.18.1 Features
      2. 7.18.2 Block Diagrams
      3. 7.18.3 Clock Source Options
      4. 7.18.4 Network Time Synchronization Inputs
    19. 7.19 Error Signaling Module
      1. 7.19.1 ESM Features
      2. 7.19.2 ESM Channel Assignments
    20. 7.20 Reset / Abort / Error Sources
    21. 7.21 Digital Windowed Watchdog
    22. 7.22 Debug Subsystem
      1. 7.22.1  Block Diagram
      2. 7.22.2  Debug Components Memory Map
      3. 7.22.3  Embedded Cross Trigger
      4. 7.22.4  JTAG Identification Code
      5. 7.22.5  Debug ROM
      6. 7.22.6  JTAG Scan Interface Timings
      7. 7.22.7  Advanced JTAG Security Module
      8. 7.22.8  Embedded Trace Macrocell (ETM-R5)
        1. 7.22.8.1 ETM TRACECLKIN Selection
        2. 7.22.8.2 Timing Specifications
      9. 7.22.9  RAM Trace Port (RTP)
        1. 7.22.9.1 RTP Features
        2. 7.22.9.2 Timing Specifications
      10. 7.22.10 Data Modification Module (DMM)
        1. 7.22.10.1 DMM Features
        2. 7.22.10.2 Timing Specifications
      11. 7.22.11 Boundary Scan Chain
  9. 8 Peripheral Information and Electrical Specifications
    1. 8.1  Enhanced Translator PWM Modules (ePWM)
      1. 8.1.1 ePWM Clocking and Reset
      2. 8.1.2 Synchronization of ePWMx Time-Base Counters
      3. 8.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 8.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 8.1.5 ePWM Synchronization with External Devices
      6. 8.1.6 ePWM Trip Zones
        1. 8.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 8.1.6.2 Trip Zone TZ4n
        3. 8.1.6.3 Trip Zone TZ5n
        4. 8.1.6.4 Trip Zone TZ6n
      7. 8.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 8.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Electrical Data/Timing
    2. 8.2  Enhanced Capture Modules (eCAP)
      1. 8.2.1 Clock Enable Control for eCAPx Modules
      2. 8.2.2 PWM Output Capability of eCAPx
      3. 8.2.3 Input Connection to eCAPx Modules
      4. 8.2.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    3. 8.3  Enhanced Quadrature Encoder (eQEP)
      1. 8.3.1 Clock Enable Control for eQEPx Modules
      2. 8.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 8.3.3 Input Connection to eQEPx Modules
      4. 8.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 8.4  12-bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 8.4.1 MibADC Features
      2. 8.4.2 Event Trigger Options
        1. 8.4.2.1 MibADC1 Event Trigger Hookup
        2. 8.4.2.2 MibADC2 Event Trigger Hookup
        3. 8.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 8.4.3 ADC Electrical and Timing Specifications
      4. 8.4.4 Performance (Accuracy) Specifications
        1. 8.4.4.1 MibADC Nonlinearity Errors
        2. 8.4.4.2 MibADC Total Error
    5. 8.5  General-Purpose Input/Output
      1. 8.5.1 Features
    6. 8.6  Enhanced High-End Timer (N2HET)
      1. 8.6.1 Features
      2. 8.6.2 N2HET RAM Organization
      3. 8.6.3 Input Timing Specifications
      4. 8.6.4 N2HET1-N2HET2 Interconnections
      5. 8.6.5 N2HET Checking
        1. 8.6.5.1 Internal Monitoring
        2. 8.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 8.6.6 Disabling N2HET Outputs
      7. 8.6.7 High-End Timer Transfer Unit (HET-TU)
        1. 8.6.7.1 Features
        2. 8.6.7.2 Trigger Connections
    7. 8.7  FlexRay Interface
      1. 8.7.1 Features
      2. 8.7.2 Electrical and Timing Specifications
      3. 8.7.3 FlexRay Transfer Unit
    8. 8.8  Controller Area Network (DCAN)
      1. 8.8.1 Features
      2. 8.8.2 241
      3. 8.8.3 Electrical and Timing Specifications
    9. 8.9  Local Interconnect Network Interface (LIN)
      1. 8.9.1 LIN Features
    10. 8.10 Serial Communication Interface (SCI)
      1. 8.10.1 Features
    11. 8.11 Inter-Integrated Circuit (I2C)
      1. 8.11.1 Features
      2. 8.11.2 I2C I/O Timing Specifications
    12. 8.12 Multibuffered / Standard Serial Peripheral Interface
      1. 8.12.1 Features
      2. 8.12.2 MibSPI Transmit and Receive RAM Organization
      3. 8.12.3 MibSPI Transmit Trigger Events
        1. 8.12.3.1 MIBSPI1 Event Trigger Hookup
        2. 8.12.3.2 MIBSPI2 Event Trigger Hookup
        3. 8.12.3.3 MIBSPI3 Event Trigger Hookup
        4. 8.12.3.4 MIBSPI4 Event Trigger Hookup
        5. 8.12.3.5 MIBSPI5 Event Trigger Hookup
      4. 8.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 8.12.5 SPI Slave Mode I/O Timings
    13. 8.13 Ethernet Media Access Controller
      1. 8.13.1 Ethernet MII Electrical and Timing Specifications
      2. 8.13.2 Ethernet RMII Electrical and Timing Specifications
      3. 8.13.3 Management Data Input/Output (MDIO)
  10. 9 Applications, Implementation, and Layout
    1. 9.1 TI Design or Reference Design
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
      2. 10.1.2 Device and Development-Support Tool Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation from Texas Instruments
      2. 10.2.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
    7. 10.7 Device Identification
      1. 10.7.1 Device Identification Code Register
      2. 10.7.2 Die Identification Registers
    8. 10.8 Module Certifications
      1. 10.8.1 FlexRay Certifications
      2. 10.8.2 DCAN Certification
      3. 10.8.3 LIN Certification
        1. 10.8.3.1 LIN Master Mode
        2. 10.8.3.2 LIN Slave Mode - Fixed Baud Rate
        3. 10.8.3.3 LIN Slave Mode - Adaptive Baud Rate
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • GWT|337
サーマルパッド・メカニカル・データ
発注情報

7.9.2 Memory Map Table

Table 7-25 Module Registers / Memories Memory Map
TARGET NAMEMEMORY
SELECT		ADDRESS RANGEFRAME
SIZE		ACTUAL
SIZE		RESPONSE FOR
ACCESS TO
UNIMPLEMENTED
LOCATIONS IN
FRAME
STARTEND
Level 2 Memories
Level 2 Flash Data Space0x0000_00000x003F_FFFF4MB4MBAbort
Level 2 RAM0x0800_00000x083F_FFFF4MB512KBAbort
Level 2 RAM ECC0x0840_00000x087F_FFFF4MB512KB
Accelerator Coherency Port
Accelerator Coherency Port0x0800_00000x087F_FFFF8MB512KBAbort
Level 1 Cache Memories
Cortex-R5F Data Cache Memory0x3000_00000x30FF_FFFF16MB32KB Abort
Cortex-R5F Instruction Cache Memory0x3100_00000x31FF_FFFF16MB32KB
External Memory Accesses
EMIF Chip Select 2 (asynchronous)0x6000_00000x63FF_FFFF64MB16MBAccess to "Reserved" space will generate Abort
EMIF Chip Select 3 (asynchronous)0x6400_00000x67FF_FFFF64MB16MB
EMIF Chip Select 4 (asynchronous)0x6800_00000x6BFF_FFFF64MB16MB
EMIF Chip Select 0 (synchronous)0x8000_00000x87FF_FFFF128MB128MB
Flash OTP, ECC, EEPROM Bank
Customer OTP, Bank00xF000_00000xF000_1FFF8KB4KBAbort
Customer OTP, Bank10xF000_20000xF000_3FFF8KB4KB
Customer OTP, EEPROM Bank0xF000_E0000xF000_FFFF8KB1KB
Customer OTP-ECC, Bank00xF004_00000xF004_03FF1KB512B
Customer OTP-ECC, Bank10xF004_04000xF004_07FF1KB512B
Customer OTP-ECC, EEPROM Bank0xF004_1C000xF004_1FFF1KB128B
TI OTP, Bank00xF008_00000xF008_1FFF8KB4KB
TI OTP, Bank10xF008_20000xF008_3FFF8KB4KB
TI OTP, EEPROM Bank0xF008_E0000xF008_FFFF8KB1KB
TI OTP-ECC, Bank00xF00C_00000xF00C_03FF1KB512B
TI OTP-ECC, Bank10xF00C_04000xF00C_07FF1KB512BAbort
TI OTP-ECC, EEPROM Bank0xF00C_1C000xF00C_1FFF1KB128B
EEPROM Bank-ECC0xF010_00000xF01F_FFFF1MB16KB
EEPROM Bank0xF020_00000xF03F_FFFF2MB128KB
Flash Data Space ECC0xF040_00000xF05F_FFFF2MB512KB
Interconnect SDC MMR
Interconnect SDC MMR0xFA00_00000xFAFF_FFFF16MB16MB
Registers/Memories under PCR2 (Peripheral Segment 2)
CPPI Memory Slave (Ethernet RAM)PCS[41]0xFC52_00000xFC52_1FFF8KB8KBAbort
CPGMAC Slave (Ethernet Slave)PS[30]-PS[31]0xFCF7_80000xFCF7_87FF2KB2KBNo Error
CPGMACSS Wrapper (Ethernet Wrapper)PS[29]0xFCF7_88000xFCF7_88FF256B256BNo Error
Ethernet MDIO InterfacePS[29]0xFCF7_89000xFCF7_89FF256B256BNo Error
ePWM1PS[28]0xFCF7_8C000xFCF7_8CFF256B256BAbort
ePWM20xFCF7_8D000xFCF7_8DFF256B256BAbort
ePWM30xFCF7_8E000xFCF7_8EFF256B256BAbort
ePWM40xFCF7_8F000xFCF7_8FFF256B256BAbort
ePWM5PS[27]0xFCF7_90000xFCF7_90FF256B256BAbort
ePWM60xFCF7_91000xFCF7_91FF256B256BAbort
ePWM70xFCF7_92000xFCF7_92FF256B256BAbort
eCAP10xFCF7_93000xFCF7_93FF256B256BAbort
eCAP2PS[26]0xFCF7_94000xFCF7_94FF256B256BAbort
eCAP30xFCF7_95000xFCF7_95FF256B256BAbort
eCAP40xFCF7_96000xFCF7_96FF256B256BAbort
eCAP50xFCF7_97000xFCF7_97FF256B256BAbort
eCAP6PS[25]0xFCF7_98000xFCF7_98FF256B256BAbort
eQEP10xFCF7_99000xFCF7_99FF256B256BAbort
eQEP20xFCF7_9A000xFCF7_9AFF256B256BAbort
PCR2 registersPPSE[4]–PPSE[5]0xFCFF_10000xFCFF_17FF2KB2KBReads return zeros, writes have no effect
NMPU (EMAC)PPSE[6]0xFCFF_18000xFCFF_18FF512B512BAbort
EMIF RegistersPPS[2]0xFCFF_E8000xFCFF_E8FF256B256BAbort
Cyclic Redundancy Checker (CRC) Module Register Frame
CRC10xFE00_00000xFEFF_FFFF16MB512KBAccesses above 0xFE000200 generate abort.
CRC20xFB00_00000xFBFF_FFFF16MB512KBAccesses above 0xFB000200 generate abort.
Memories under User PCR3 (Peripheral Segment 3)
MIBSPI5 RAMPCS[5]0xFF0A_00000xFF0B_FFFF128KB2KBAbort for accesses above 2KB
MIBSPI4 RAMPCS[3]0xFF06_00000xFF07_FFFF128KB2KBAbort for accesses above 2KB
MIBSPI3 RAMPCS[6]0xFF0C_00000xFF0D_FFFF128KB2KBAbort for accesses above 2KB
MIBSPI2 RAMPCS[4]0xFF08_00000xFF09_FFFF128KB2KBAbort for accesses above 2KB
MIBSPI1 RAMPCS[7]0xFF0E_00000xFF0F_FFFF128KB4KBAbort for accesses above 4KB
DCAN4 RAMPCS[12]0xFF18_00000xFF19_FFFF128KB8KBAbort generated for accesses beyond offset 0x2000
DCAN3 RAMPCS[13]0xFF1A_00000xFF1B_FFFF128KB8KBAbort generated for accesses beyond offset 0x2000
DCAN2 RAMPCS[14]0xFF1C_00000xFF1D_FFFF128KB8KBAbort generated for accesses beyond offset 0x2000
DCAN1 RAMPCS[15]0xFF1E_00000xFF1F_FFFF128KB8KBAbort generated for accesses beyond offset 0x2000.
MIBADC2 RAMPCS[29]0xFF3A_00000xFF3B_FFFF128KB8KBWrap around for accesses to unimplemented address offsets lower than 0x1FFF.
MIBADC1 RAMPCS[31]0xFF3E_00000xFF3F_FFFF128KB8KBWrap around for accesses to unimplemented address offsets lower than 0x1FFF.
MIBADC1 Look-UP Table384 bytesLook-Up Table for ADC1 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generation for accesses beyond offset 0x4000.
NHET2 RAMPCS[34]0xFF44_00000xFF45_FFFF128KB16KBWrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
NHET1 RAMPCS[35]0xFF46_00000xFF47_FFFF128KB16KBWrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
HET TU2 RAMPCS[38]0xFF4C_00000xFF4D_FFFF128KB1KBAbort
HET TU1 RAMPCS[39]0xFF4E_00000xFF4F_FFFF128KB1KBAbort
FlexRay TU RAMPCS[40]0xFF50_00000xFF51_FFFF128KB1KBAbort
CoreSight Debug Components
CoreSight Debug ROMCSCS[0]0xFFA0_00000xFFA0_0FFF4KB4KBReads return zeros, writes have no effect
Cortex-R5F DebugCSCS[1]0xFFA0_10000xFFA0_1FFF4KB4KBReads return zeros, writes have no effect
ETM-R5CSCS[2]0xFFA0_20000xFFA0_2FFF4KB4KBReads return zeros, writes have no effect
CoreSight TPIUCSCS[3]0xFFA0_30000xFFA0_3FFF4KB4KBReads return zeros, writes have no effect
POMCSCS[4]0xFFA0_40000xFFA0_4FFF4KB4KBReads return zeros, writes have no effect
CTI1CSCS[7]0xFFA0_70000xFFA0_7FFF4KB4KBReads return zeros, writes have no effect
CTI3CSCS[9]0xFFA0_90000xFFA0_9FFF4KB4KBReads return zeros, writes have no effect
CTI4CSCS[10]0xFFA0_A0000xFFA0_AFFF4KB4KBReads return zeros, writes have no effect
CSTFCSCS[11]0xFFA0_B0000xFFA0_BFFF4KB4KBReads return zeros, writes have no effect
Registers under PCR3 (Peripheral Segment 3)
PCR3 registersPS[31:30]0xFFF7_80000xFFF7_87FF2KB2KBReads return zeros, writes have no effect
FTUPS[23]0xFFF7_A0000xFFF7_A1FF512B512BReads return zeros, writes have no effect
HTU1PS[22]0xFFF7_A4000xFFF7_A4FF256B256BAbort
HTU2PS[22]0xFFF7_A5000xFFF7_A5FF256B256BAbort
NHET1PS[17]0xFFF7_B8000xFFF7_B8FF256B256BReads return zeros, writes have no effect
NHET2PS[17]0xFFF7_B9000xFFF7_B9FF256B256BReads return zeros, writes have no effect
GIOPS[16]0xFFF7_BC000xFFF7_BCFF256B256BReads return zeros, writes have no effect
MIBADC1PS[15]0xFFF7_C0000xFFF7_C1FF512B512BReads return zeros, writes have no effect
MIBADC2PS[15]0xFFF7_C2000xFFF7_C3FF512B512BReads return zeros, writes have no effect
FlexRayPS[12]+PS[13]0xFFF7_C8000xFFF7_CFFF2KB2KBReads return zeros, writes have no effect
I2C1PS[10]0xFFF7_D4000xFFF7_D4FF256B256BReads return zeros, writes have no effect
I2C2PS[10]0xFFF7_D5000xFFF7_D5FF256B256BReads return zeros, writes have no effect
DCAN1PS[8]0xFFF7_DC000xFFF7_DDFF512B512BReads return zeros, writes have no effect
DCAN2PS[8]0xFFF7_DE000xFFF7_DFFF512B512BReads return zeros, writes have no effect
DCAN3PS[7]0xFFF7_E0000xFFF7_E1FF512B512BReads return zeros, writes have no effect
DCAN4PS[7]0xFFF7_E2000xFFF7_E3FF512B512BReads return zeros, writes have no effect
LIN1PS[6]0xFFF7_E4000xFFF7_E4FF256B256BReads return zeros, writes have no effect
SCI3PS[6]0xFFF7_E5000xFFF7_E5FF256B256BReads return zeros, writes have no effect
LIN2PS[6]0xFFF7_E6000xFFF7_E6FF256B256BReads return zeros, writes have no effect
SCI4PS[6]0xFFF7_E7000xFFF7_E7FF256B256BReads return zeros, writes have no effect
MibSPI1PS[2]0xFFF7_F4000xFFF7_F5FF512B512BReads return zeros, writes have no effect
MibSPI2PS[2]0xFFF7_F6000xFFF7_F7FF512B512BReads return zeros, writes have no effect
MibSPI3PS[1]0xFFF7_F8000xFFF7_F9FF512B512BReads return zeros, writes have no effect
MibSPI4PS[1]0xFFF7_FA000xFFF7_FBFF512B512BReads return zeros, writes have no effect
MibSPI5PS[0]0xFFF7_FC000xFFF7_FDFF512B512BReads return zeros, writes have no effect
System Modules Control Registers and Memories under PCR1 (Peripheral Segment 1)
DMA RAMPPCS[0]0xFFF8_00000xFFF8_0FFF4KB4KBAbort
VIM RAMPPCS[2]0xFFF8_20000xFFF8_2FFF4KB4KBWrap around for accesses to unimplemented address offsets lower than 0x2FFF.
RTP RAMPPCS[3]0xFFF8_30000xFFF8_3FFF4KB4KBAbort
Flash WrapperPPCS[7]0xFFF8_70000xFFF8_7FFF4KB4KBAbort
eFuse Farm ControllerPPCS[12]0xFFF8_C0000xFFF8_CFFF4KB4KBAbort
Power Domain Control (PMM)PPSE[0]0xFFFF_00000xFFFF_01FF512B512BAbort
FMTM
Note: This module is only used by TI during test		PPSE[1]0xFFFF_04000xFFFF_05FF512B512BReads return zeros, writes have no effect
STC2 (NHET1/2)PPSE[2]0xFFFF_08000xFFFF_08FF256B256BReads return zeros, writes have no effect
SCMPPSE[2]0xFFFF_0A000xFFFF_0AFF256B256BAbort
EPCPPSE[3]0xFFFF_0C000xFFFF_0FFF1KB1KBAbort
PCR1 registersPPSE[4]–PPSE[5]0xFFFF_10000xFFFF_17FF2KB2KBReads return zeros, writes have no effect
NMPU (PS_SCR_S)PPSE[6]0xFFFF_18000xFFFF_19FF512B512BAbort
NMPU (DMA Port A)PPSE[6]0xFFFF_1A000xFFFF_1BFF512B512BAbort
Pin Mux Control (IOMM)PPSE[7]0xFFFF_1C000xFFFF_1FFF2KB1KBReads return zeros, writes have no effect
System Module - Frame 2 (see the TRM SPNU563)PPS[0]0xFFFF_E1000xFFFF_E1FF256B256BReads return zeros, writes have no effect
PBISTPPS[1]0xFFFF_E4000xFFFF_E5FF512B512BReads return zeros, writes have no effect
STC1 (Cortex-R5F)PPS[1]0xFFFF_E6000xFFFF_E6FF256B256BReads return zeros, writes have no effect
DCC1PPS[3]0xFFFF_EC000xFFFF_ECFF256B256BReads return zeros, writes have no effect
DMAPPS[4]0xFFFF_F0000xFFFF_F3FF1KB1KBAbort
DCC2PPS[5]0xFFFF_F4000xFFFF_F4FF256B256BReads return zeros, writes have no effect
ESM registerPPS[5]0xFFFF_F5000xFFFF_F5FF256B256BReads return zeros, writes have no effect
CCM-R5FPPS[5]0xFFFF_F6000xFFFF_F6FF256B256BReads return zeros, writes have no effect
DMMPPS[5]0xFFFF_F7000xFFFF_F7FF256B256BReads return zeros, writes have no effect
L2RAMWPPS[6]0xFFFF_F9000xFFFF_F9FF256B256BAbort
RTPPPS[6]0xFFFF_FA000xFFFF_FAFF256B256BReads return zeros, writes have no effect
RTI + DWWDPPS[7]0xFFFF_FC000xFFFF_FCFF256B256BReads return zeros, writes have no effect
VIMPPS[7]0xFFFF_FD000xFFFF_FEFF512B512BReads return zeros, writes have no effect
System Module - Frame 1 (see the TRM SPNU563)PPS[7]0xFFFF_FF000xFFFF_FFFF256B256BReads return zeros, writes have no effect