SLVSDG3C March   2016  – December 2016 TPD1E01B04

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  IEC 61000-4-2 ESD Protection
      2. 7.3.2  IEC 61000-4-4 EFT Protection
      3. 7.3.3  IEC 61000-4-5 Surge Protection
      4. 7.3.4  IO Capacitance
      5. 7.3.5  DC Breakdown Voltage
      6. 7.3.6  Ultra Low Leakage Current
      7. 7.3.7  Low ESD Clamping Voltage
      8. 7.3.8  Supports High Speed Interfaces
      9. 7.3.9  Industrial Temperature Range
      10. 7.3.10 Easy Flow-Through Routing Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Electrical fast transient IEC 61000-4-5 (5/50 ns) 80 A
Peak pulse IEC 61000-4-5 power (tp - 8/20 µs) 27 W
IEC 61000-4-5 current (tp - 8/20 µs) 2.5 A
TA Operating free-air temperature –40 125 °C
Tstg Storage temperature –65 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings—IEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±15000 V
IEC 61000-4-2 air-gap discharge ±17000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO Input pin voltage –3.6 3.6 V
TA Operating free-air temperature –40 125 °C

6.5 Thermal Information

THERMAL METRIC(1) TPD1E01B04 UNIT
DPL (X2SON) DPY (X1SON)
2 PINS 2 PINS
RθJA Junction-to-ambient thermal resistance 582 442.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 264.5 243.8 °C/W
RθJB Junction-to-board thermal resistance 394.4 162.5 °C/W
ψJT Junction-to-top characterization parameter 36.4 154.1 °C/W
ψJB Junction-to-board characterization parameter 394.4 163.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 nA –3.6 3.6 V
VBRF Breakdown voltage, IO pin to GND Measured as the maximum voltage before device snaps back into VHOLD voltage 6.4 V
VBRR Breakdown voltage, GND to IO pin –6.4 V
VHOLD Holding voltage IIO = 1 mA, TA = 25°C 5 5.9 6.5 V
VCLAMP Clamping voltage IPP = 1 A, TLP, from IO to GND 7 V
IPP = 5 A, TLP, from IO to GND 9.2
IPP = 16 A, TLP, from IO to GND 15
IPP = 1 A, TLP, from GND to IO 7
IPP = 5 A, TLP, from GND to IO 9.2
IPP = 16 A, TLP, from GND to IO 15
ILEAK Leakage current, IO to GND VIO = ±2.5 V 10 nA
RDYN Dynamic resistance IO to GND 0.57 Ω
GND to IO 0.57
CL Line capacitance DPL Package VIO = 0 V, f = 1 MHz, IO to GND
TA = 25°C 		0.18 0.20 pF
DPY Package 0.20 0.23

6.7 Typical Characteristics

TPD1E01B04 D001_SLVSDG3.gif
A.
Figure 1. Positive TLP Curve
TPD1E01B04 D003_SLVSDG3.gif Figure 3. 8-kV IEC Waveform
TPD1E01B04 D005_SLVSDG3.gif Figure 5. Surge Curve (tp = 8/20µs), IO pin to GND
TPD1E01B04 D006_SLVSDG3.gif Figure 7. Capacitance vs. Bias Voltage (DPY Package)
TPD1E01B04 D008_SLVSDG3.gif Figure 9. DC Voltage Sweep I-V Curve
TPD1E01B04 D010_SLVSDG3.gif Figure 11. Insertion Loss
TPD1E01B04 D002_SLVSDG3.gif
A.
Figure 2. Negative TLP Curve
TPD1E01B04 D004_SLVSDG3.gif Figure 4. –8-kV IEC Waveform
TPD1E01B04 D006_SLVSDG3.gif Figure 6. Capacitance vs. Bias Voltage (DPL Package)
TPD1E01B04 D007_SLVSDG3.gif Figure 8. Leakage Current vs. Temperature
TPD1E01B04 D009_SLVSDG3.gif Figure 10. Capacitance vs. Frequency
TPD1E01B04 USB3.1_Eye_Unpopulated.png Figure 12. USB3.1 Gen 2 10-Gbps Eye Diagram
(Bare Board)
TPD1E01B04 USB3.1_Eye_Populated_TPD1E01B04.png Figure 13. USB3.1 Gen 2 10-Gbps Eye Diagram
(with TPD1E01B04DPL)