JAJSCG6 September   2016 TPL5010-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 WAKE
      2. 8.3.2 DONE
      3. 8.3.3 RSTn
    4. 8.4 Device Functional Modes
      1. 8.4.1 Startup
      2. 8.4.2 Normal Operating Mode
    5. 8.5 Programming
      1. 8.5.1 Configuring the WAKE Interval with the DELAY/M_RST Pin
      2. 8.5.2 Manual Reset
        1. 8.5.2.1 DELAY/M_RST
        2. 8.5.2.2 Circuitry
      3. 8.5.3 Timer Interval Selection Using External Resistance
      4. 8.5.4 Quantization Error
      5. 8.5.5 Error Due to Real External Resistance
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage (VDD-GND) –0.3 6.0 V
Input voltage at any pin(3) –0.3 VDD + 0.3 V
Input current on any pin –5 5 mA
Tstg Storage temperature –65 150 °C
TJ Junction temperature(2) 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
(3) The voltage between any two pins should not exceed 6V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model, per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q10-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage (VDD-GND) 1.8 5.5 V
Temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPL5010-Q1 UNIT
SOT23
6 PINS
RθJA Junction-to-ambient thermal resistance 163 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 26 °C/W
RθJB Junction-to-board thermal resistance 57 °C/W
ψJT Junction-to-top characterization parameter 7.5 °C/W
ψJB Junction-to-board characterization parameter 57 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

TA= 25°C, VDD-GND=2.5 V (unless otherwise stated)(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
POWER SUPPLY
IDD Supply current(4) Operation mode 35 50 nA
Digital conversion of external resistance (Rext) 200 400 µA
TIMER
tIP Time interval period(5) 1650 selectable time Intervals Min time interval 100 ms
Max time interval 7200 s
Time interval setting accuracy(7) Excluding the precision of Rext ±0.6%
Timer interval setting accuracy over supply voltage 1.8 V ≤ VDD ≤ 5.5 V ±25 ppm/V
tOSC Oscillator accuracy –0.5% 0.5%
Oscillator accuracy over temperature(5) -40°C ≤ TA ≤ 125°C 150 ppm/°C
Oscillator accuracy over supply voltage(5) 1.8 V ≤ VDD ≤ 5.5 V ±0.4 %/V
Oscillator accuracy over life time(6) 0.24%
tDONE Minimum DONE pulse width (5) 100 ns
tRSTn RSTn pulse width 320 ms
tWAKE WAKE pulse width 20 ms
t_Rext Time to convert Rext(5) 100 ms
DIGITAL LOGIC LEVELS
VIH Minimum logic high threshold DONE pin 0.7 × VDD V
VIL Maximum logic low threshold DONE pin 0.3 × VDD V
VOH Logic output high-level WAKE pin Iout = 100 µA VDD – 0.3 V
Iout = 1 mA VDD – 0.7 V
VOL Logic output low-level WAKE pin Iout = –100 µA 0.3 V
Iout = –1 mA 0.7 V
VOLRSTn RSTn logic output low-level IOL= –1 mA 0.3 V
IOHRSTn RSTn high-level output current VOHRSTn = VDD 1 nA
VIHM_RST Minimum logic high threshold DELAY/M_RST pin(5) 1.5 V
(1) Values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD.
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) Operational life time test procedure equivalent to 10 years.
(7) The accuracy for time interval settings below 1 second is ±100 ms.

7.6 Timing Requirements

MIN(3) NOM(4) MAX(3) UNIT
trRSTn Rise Time RSTn (2) Capacitive load 50 pF, Rpull-up 100 kΩ 11 µs
tfRSTn Fall time RSTn (2) Capacitive load 50 pF, Rpull-up 100 kΩ 50 ns
trWAKE Rise time WAKE (2) Capacitive load 50 pF 50 ns
tfWAKE Fall time WAKE (2) Capacitive load 50 pF 50 ns
tDDONE DONE to RSTn or WAKE to DONE delay Min delay(1) 100 ns
Max delay (1) tIP–20 ms
tM_RST Minimum valid manual reset (2) Observation time 30 ms 20 ms
tDB De-bounce manual reset 20 ms
(1) In case of RSTn from its falling edge, in case of WAKE, from its rising edge.
(2) This parameter is specified by design and/or characterization and is not tested in production.
(3) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
TPL5010-Q1 TIMING_5010_rev4.gif Figure 1. TPL5010-Q1 Timing

7.7 Typical Characteristics

TPL5010-Q1 D001_SNAS679.gif
Figure 2. IDD vs VDD
TPL5010-Q1 D020_SNAS679.gif
1.
Figure 4. Oscillator Accuracy vs VDD
TPL5010-Q1 D031_SNAS650.gif
Figure 6. IDD vs Time
TPL5010-Q1 D002_SNAS679.gif
Figure 3. IDD vs Temperature
TPL5010-Q1 D021_SNAS679.gif
1.
Figure 5. Oscillator Accuracy vs Temperature
TPL5010-Q1 D022_SNAS651.gif
number of observations > 20000 1 s < tIP ≤ 7200 s
Figure 7. Time Interval Setting Accuracy