SLVSBJ0F August   2012  – August 2016 TPS22965

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics—VBIAS = 5 V
    6. 7.6 Electrical Characteristics—VBIAS = 2.5 V
    7. 7.7 Switching Characteristics
    8. 7.8 Typical DC Characteristics
    9. 7.9 Typical Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Adjustable Rise Time
      2. 9.3.2 Quick Output Discharge (QOD) (Optional)
      3. 9.3.3 Low Power Consumption During Off State
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ON and OFF Control
      2. 10.1.2 Input Capacitor (Optional)
      3. 10.1.3 Output Capacitor (Optional)
      4. 10.1.4 VIN and VBIAS Voltage Range
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
        2. 10.2.2.2 Thermal Considerations
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.1.1 ON and OFF Control

The ON pin controls the state of the switch. Asserting ON high enables the switch. ON is active high and has a low threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard GPIO logic thresholds. It can be used with any microcontroller with 1.2 V or higher GPIO voltage. This pin cannot be left floating and must be driven either high or low for proper functionality.

10.1.2 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1-µF ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop during high current applications. When switching heavy loads, it is recommended to have an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.

10.1.3 Output Capacitor (Optional)

Becuase of the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN dip caused by inrush currents during startup; however, a 10 to 1 ratio for capacitance is not required for proper functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more VIN dip upon turn-on due to inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer rise time (see the Adjustable Rise Time section).

10.1.4 VIN and VBIAS Voltage Range

For optimal RON performance, make sure VIN ≤ VBIAS. The device is still functional if VIN > VBIAS but it exhibits RON greater than what is listed in the Electrical Characteristics—VBIAS = 5 V table. See Figure 34 for an example of a typical device. Notice the increasing RON as VIN exceeds VBIAS voltage. Never exceed the maximum voltage rating for VIN and VBIAS.

TPS22965 G022_lvsbj0.gif
TA = 25 °C IOUT = –200 mA
Figure 34. RON vs VIN

10.2 Typical Application

This application demonstrates how the TPS22965x can be used to power downstream modules.

TPS22965 typ_app_slvsbj0.gif Figure 35. Powering a Downstream Module

10.2.1 Design Requirements

Table 3 shows the design parameters.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VIN 3.3 V
VBIAS 5 V
CL 22 µF
Maximum Acceptable Inrush Current 400 mA

10.2.2 Detailed Design Procedure

10.2.2.1 Inrush Current

When the switch is enabled, the output capacitors must be charged up from 0 V to the set value (3.3 V in this example). This charge arrives in the form of inrush current. Inrush current can be calculated using Equation 2.

Equation 2. Inrush Current = C × dV/dt

where

  • C is the output capacitance
  • dV is the output voltage
  • dt is the rise time

The TPS22965x offers adjustable rise time for VOUT. This feature allows the user to control the inrush current during turn-on. The appropriate rise time can be calculated using the design requirements and the inrush current equation. See Equation 3 and Equation 4.

Equation 3. 400 mA = 22 µF × 3.3 V/dt
Equation 4. dt = 181.5 µs

To ensure an inrush current of less than 400 mA, choose a CT value that yields a rise time of more than 181.5 µs. See the oscilloscope captures in the Application Curves section for an example of how the CT capacitor can be used to reduce inrush current.

10.2.2.2 Thermal Considerations

The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 5 as a guideline:

Equation 5. TPS22965 eq2_lvsbh4.gif

where

  • PD(max) is the maximum allowable power dissipation
  • TJ(max) is the maximum allowable junction temperature (125°C for the TPS22965x)
  • TA is the ambient temperature of the device
  • ΘJA = junction to air thermal impedance. See the Thermal Information table. This parameter is highly dependent upon board layout.

See Figure 38, notice that the thermal vias are located under the exposed thermal pad of the device. This allows for thermal diffusion away from the device.

10.2.3 Application Curves

TPS22965 TPS22965_Inrush1.png
VBIAS = 5 V VIN = 3.3 V CL = 22 µF
Figure 36. Inrush Current with CT = 0 pF
TPS22965 TPS22965_Inrush2.png
VBIAS = 5 V VIN = 3.3 V CL = 22 µF
Figure 37. Inrush Current with CT = 220 pF