SLVSCL4B August   2014  – September 2014 TPS22994

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Recommended Operating Conditions
    2. 8.2 Absolute Maximum Ratings
    3. 8.3 Handling Ratings
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics, VBIAS = 7.2 V
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Operating Frequency
      2. 9.3.2  SDA/SCL Pin Configuration
      3. 9.3.3  Address (ADDx) Pin Configuration
      4. 9.3.4  On-Delay Control
      5. 9.3.5  Slew Rate Control
      6. 9.3.6  Quick Output Discharge (QOD) Control
      7. 9.3.7  Mode Registers
      8. 9.3.8  SwitchALL™ Command
      9. 9.3.9  VDD Supply For I2C Operation
      10. 9.3.10 Input Capacitor (Optional)
      11. 9.3.11 Output Capacitor (Optional)
      12. 9.3.12 I2C Protocol
        1. 9.3.12.1 Start and Stop Bit
        2. 9.3.12.2 Auto-increment Bit
        3. 9.3.12.3 Write Command
        4. 9.3.12.4 Read Command
        5. 9.3.12.5 SwitchALLTM Command
    4. 9.4 Device Functional Modes
      1. 9.4.1 I2C Control
      2. 9.4.2 GPIO Control
    5. 9.5 Register Map
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Capacitor (Optional)
      2. 10.1.2 Output Capacitor (Optional)
      3. 10.1.3 Switch from GPIO Control to I2C Control (and vice versa)
      4. 10.1.4 Configuration of Configuration Registers
        1. 10.1.4.1 Single Register Configuration
        2. 10.1.4.2 Multi-register Configuration (Consecutive Registers)
      5. 10.1.5 Configuration of Mode Registers
      6. 10.1.6 Turn-on/Turn-off of Channels
    2. 10.2 Typical Application
      1. 10.2.1 Tying Multiple Channels in Parallel
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Cold Boot Programming of All Registers
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Power Sequencing Without I2C
        1. 10.2.3.1 Design Requirements
          1. 10.2.3.1.1 Reading From the Registers
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 VIN to VOUT Voltage Drop
          2. 10.2.3.2.2 Inrush Current
        3. 10.2.3.3 Application Curves
  11. 11Layout
    1. 11.1 Board Layout
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Board Layout

  • VINx and VOUTx traces should be as short and wide as possible to accommodate for high current.
  • Use vias under the exposed thermal pad for thermal relief for high current operation.
  • The VINx terminals should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device terminals as possible.
  • The VOUTx terminals should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating. This capacitor should be placed as close to the device terminals as possible.
  • The VBIAS terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.
  • The VDD terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.
  • ADDx pins should be tied high to VDD through a pull-up resistor or tied low to GND through a pull-down resistor.

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable power dissipation, PD(max) for a given output current and ambient temperature, use the following equation:

Equation 4. eq2_lvsbh4.gif

Where:

PD(max) = maximum allowable power dissipation
TJ(max) = maximum allowable junction temperature (125°C for the TPS22994)
TA = ambient temperature of the device
ΘJA = junction to air thermal impedance. See Thermal Information section. This parameter is highly dependent upon board layout.

The figure below shows an example of a layout.

Layout.gif