JAJSDX9C June   2017  – November 2018 TPS2373

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD Auxiliary Power Detect
      2. 7.3.2  PG Power Good (Converter Enable) Pin Interface
      3. 7.3.3  CLSA and CLSB Classification
      4. 7.3.4  DEN Detection and Enable
      5. 7.3.5  Internal Pass MOSFET
      6. 7.3.6  TPH, TPL and BT PSE Type Indicators
      7. 7.3.7  VC_IN, VC_OUT, UVLO_SEL, and Advanced PWM Startup
      8. 7.3.8  AMPS_CTL, MPS_DUTY and Automatic MPS
      9. 7.3.9  VDD Supply Voltage
      10. 7.3.10 VSS
      11. 7.3.11 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Inrush and Startup
      7. 7.4.7  Maintain Power Signature
      8. 7.4.8  Advanced Startup and Converter Operation
      9. 7.4.9  PD Hotswap Operation
      10. 7.4.10 Startup and Power Management, PG and TPH, TPL, BT
      11. 7.4.11 Adapter ORing
      12. 7.4.12 Using DEN to Disable PoE
      13. 7.4.13 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  APD Pin Divider Network RAPD1, RAPD2
        7. 8.2.2.7  Opto-isolators for TPH, TPL and BT
        8. 8.2.2.8  VC Input and Output, CVCIN and CVCOUT
        9. 8.2.2.9  UVLO Select, UVLO_SEL
        10. 8.2.2.10 Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        11. 8.2.2.11 Internal Voltage Reference, RREF
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGW|20
サーマルパッド・メカニカル・データ
発注情報

6.6 Typical Characteristics

TPS2373 D001_SLUSCD1.gif
Figure 1. Detection Bias Current vs PoE Voltage
TPS2373 D007_SLUSCD1.gif
Figure 3. APD Threshold Voltage vs Temperature, TPS2373-4
TPS2373 D004_SLUSCD1.gif
Figure 5. Classification Upper Threshold vs Temperature
TPS2373 D006_SLUSCD1.gif
Figure 7. Mark Resistance vs Temperature
TPS2373 D009_SLUSCD1.gif
Figure 9. PoE Current Limit vs Temperature, TPS2373-4
TPS2373 D011_SLUSCD1.gif
Figure 11. Inrush Termination Threshold vs Temperature, TPS2373-4
TPS2373 D013_SLUSCD1.gif
Figure 13. UVLO Rising Threshold vs Temperature
TPS2373 D015_SLUSCD1.gif
Figure 15. Converter Startup Voltage vs Current
TPS2373 D018_SLUSCD1.gif
Figure 17. Converter Startup Current vs Input Voltage
TPS2373 D020_SLUSCD1.gif
Figure 19. VC_IN Threshold vs Temperature
TPS2373 D002_SLUSCD1.gif
Figure 2. IVDD Bias Current vs Voltage
TPS2373 D003_SLUSCD1.gif
Figure 4. Classification Lower Threshold vs Temperature
TPS2373 D005_SLUSCD1.gif
Figure 6. Mark Reset Threshold vs Temperature
TPS2373 D008_SLUSCD1.gif
Figure 8. Pass FET Resistance vs Temperature, TPS2373-4
TPS2373 D010_SLUSCD1.gif
Figure 10. PoE Inrush Current Limit vs Temperature, TPS2373-4
TPS2373 D012_SLUSCD1.gif
Figure 12. Inrush Time Delay vs Temperature
TPS2373 D014_SLUSCD1.gif
Figure 14. UVLO Falling Threshold vs Temperature
TPS2373 D017_SLUSCD1.gif
Figure 16. Converter Startup Current vs Input Voltage
TPS2373 D019_SLUSCD1.gif
Figure 18. VC_OUT UVLO vs Temperature
TPS2373 D021_SLUSCD1.gif
Figure 20. VC Switch Resistance vs Temperature