JAJSEO7I October   2008  – December 2017 TPS23754 , TPS23754-1 , TPS23756

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      TPS23754を使用する高効率コンバータ
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics: PoE and Control
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  APD
      2. 8.3.2  BLNK
      3. 8.3.3  CLS
      4. 8.3.4  Current Sense (CS)
      5. 8.3.5  Control (CTL)
      6. 8.3.6  Detection and Enable (DEN)
      7. 8.3.7  DT
      8. 8.3.8  Frequency and Synchronization (FRS)
      9. 8.3.9  GATE
      10. 8.3.10 GAT2
      11. 8.3.11 PPD
      12. 8.3.12 RTN, ARTN, COM
      13. 8.3.13 T2P
      14. 8.3.14 VB
      15. 8.3.15 VC
      16. 8.3.16 VDD
      17. 8.3.17 VDD1
      18. 8.3.18 VSS
      19. 8.3.19 PowerPAD
    4. 8.4 Device Functional Modes
      1. 8.4.1 PoE Overview
        1. 8.4.1.1  Threshold Voltages
        2. 8.4.1.2  PoE Start-Up Sequence
        3. 8.4.1.3  Detection
        4. 8.4.1.4  Hardware Classification
        5. 8.4.1.5  Inrush and Start-Up
        6. 8.4.1.6  Maintain Power Signature
        7. 8.4.1.7  Start-Up and Converter Operation
        8. 8.4.1.8  PD Hotswap Operation
        9. 8.4.1.9  Converter Controller Features
        10. 8.4.1.10 Bootstrap Topology
        11. 8.4.1.11 Current Slope Compensation and Current Limit
        12. 8.4.1.12 Blanking – RBLNK
        13. 8.4.1.13 Dead Time
        14. 8.4.1.14 FRS and Synchronization
        15. 8.4.1.15 T2P, Start-Up, and Power Management
        16. 8.4.1.16 Thermal Shutdown
        17. 8.4.1.17 Adapter ORing
        18. 8.4.1.18 PPD ORing Features
        19. 8.4.1.19 Using DEN to Disable PoE
        20. 8.4.1.20 ORing Challenges
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bridges and Schottky Diodes
        2. 9.2.2.2  Protection, D1
        3. 9.2.2.3  Capacitor, C1
        4. 9.2.2.4  Detection Resistor, RDEN
        5. 9.2.2.5  Classification Resistor, RCLS
        6. 9.2.2.6  Dead Time Resistor, RDT
        7. 9.2.2.7  Switching Transformer Considerations and RVC
        8. 9.2.2.8  Special Switching MOSFET Considerations
        9. 9.2.2.9  Thermal Considerations and OTSD
        10. 9.2.2.10 APD Pin Divider Network, RAPD1, RAPD2
        11. 9.2.2.11 PPD Pin Divider Network, RPPD1, RPPD2
        12. 9.2.2.12 Setting Frequency (RFRS) and Synchronization
        13. 9.2.2.13 Current Slope Compensation
        14. 9.2.2.14 Blanking Period, RBLNK
        15. 9.2.2.15 Estimating Bias Supply Requirements and CVC
        16. 9.2.2.16 T2P Pin Interface
        17. 9.2.2.17 Advanced ORing Techniques
        18. 9.2.2.18 Soft Start
        19. 9.2.2.19 Frequency Dithering for Conducted Emissions Control
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 ESD
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • PWP|20
サーマルパッド・メカニカル・データ
発注情報

Dead Time

The TPS23754 device features two switching MOSFET gate drivers to ease implementation of high-efficiency topologies. Specifically, these include active (primary) clamp topologies and those with synchronous drivers that are hard-driven by the control circuit. In all cases, there is a need to assure that both driven MOSFETs are not on at the same time. The DT pin programs a fixed time period delay between the turnon of one gate driver until the turnon of the next. This feature is an improvement over the repeatability and accuracy of discrete solutions while eliminating a number of discrete parts on the board. Converter efficiency is easily tuned with this one repeatable adjustment. The programmed dead time is the same for both GATE-to-GAT2 and GAT2-to-GATE transitions. The dead time is triggered from internal signals that are several stages back in the driver to eliminate the effects of gate loading on the period; however, the observed and actual dead-time will be somewhat dependent on the gate loading. The turnoff of GAT2 coincides with the start of the internal clock period.

DT may be used to disable GAT2, which goes to a high-impedance state.

GATE’s phase turns the main switch on when it transitions high, and off when it transitions low. GAT2’s phase turns the second switch off when it transitions high, and on when it transitions low. Both switches should be off when GAT2 is high and GATE is low. The signal phasing is shown in Figure 1. Many topologies that use secondary-side synchronous rectifiers also use N-Channel MOSFETs driven through a gate-drive transformer. The proper signal phase for these rectifiers may be achieved by inverting the phasing of the secondary winding (swapping the leads). Use of the two gate drives is shown in Figure 27 and Figure 27.