JAJSEO7I October   2008  – December 2017 TPS23754 , TPS23754-1 , TPS23756

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      TPS23754を使用する高効率コンバータ
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics: PoE and Control
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  APD
      2. 8.3.2  BLNK
      3. 8.3.3  CLS
      4. 8.3.4  Current Sense (CS)
      5. 8.3.5  Control (CTL)
      6. 8.3.6  Detection and Enable (DEN)
      7. 8.3.7  DT
      8. 8.3.8  Frequency and Synchronization (FRS)
      9. 8.3.9  GATE
      10. 8.3.10 GAT2
      11. 8.3.11 PPD
      12. 8.3.12 RTN, ARTN, COM
      13. 8.3.13 T2P
      14. 8.3.14 VB
      15. 8.3.15 VC
      16. 8.3.16 VDD
      17. 8.3.17 VDD1
      18. 8.3.18 VSS
      19. 8.3.19 PowerPAD
    4. 8.4 Device Functional Modes
      1. 8.4.1 PoE Overview
        1. 8.4.1.1  Threshold Voltages
        2. 8.4.1.2  PoE Start-Up Sequence
        3. 8.4.1.3  Detection
        4. 8.4.1.4  Hardware Classification
        5. 8.4.1.5  Inrush and Start-Up
        6. 8.4.1.6  Maintain Power Signature
        7. 8.4.1.7  Start-Up and Converter Operation
        8. 8.4.1.8  PD Hotswap Operation
        9. 8.4.1.9  Converter Controller Features
        10. 8.4.1.10 Bootstrap Topology
        11. 8.4.1.11 Current Slope Compensation and Current Limit
        12. 8.4.1.12 Blanking – RBLNK
        13. 8.4.1.13 Dead Time
        14. 8.4.1.14 FRS and Synchronization
        15. 8.4.1.15 T2P, Start-Up, and Power Management
        16. 8.4.1.16 Thermal Shutdown
        17. 8.4.1.17 Adapter ORing
        18. 8.4.1.18 PPD ORing Features
        19. 8.4.1.19 Using DEN to Disable PoE
        20. 8.4.1.20 ORing Challenges
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bridges and Schottky Diodes
        2. 9.2.2.2  Protection, D1
        3. 9.2.2.3  Capacitor, C1
        4. 9.2.2.4  Detection Resistor, RDEN
        5. 9.2.2.5  Classification Resistor, RCLS
        6. 9.2.2.6  Dead Time Resistor, RDT
        7. 9.2.2.7  Switching Transformer Considerations and RVC
        8. 9.2.2.8  Special Switching MOSFET Considerations
        9. 9.2.2.9  Thermal Considerations and OTSD
        10. 9.2.2.10 APD Pin Divider Network, RAPD1, RAPD2
        11. 9.2.2.11 PPD Pin Divider Network, RPPD1, RPPD2
        12. 9.2.2.12 Setting Frequency (RFRS) and Synchronization
        13. 9.2.2.13 Current Slope Compensation
        14. 9.2.2.14 Blanking Period, RBLNK
        15. 9.2.2.15 Estimating Bias Supply Requirements and CVC
        16. 9.2.2.16 T2P Pin Interface
        17. 9.2.2.17 Advanced ORing Techniques
        18. 9.2.2.18 Soft Start
        19. 9.2.2.19 Frequency Dithering for Conducted Emissions Control
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 ESD
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • PWP|20
サーマルパッド・メカニカル・データ
発注情報

Estimating Bias Supply Requirements and CVC

The bias supply (VC) power requirements determine the CVC sizing and frequency of hiccup during a fault. The first step is to determine the power and current requirements of the power supply control, then use this to select CVC. The control current draw will be assumed constant with voltage to simplify the estimate, resulting in an approximate value.

First determine the switching MOSFET gate drive power.

  1. Let VQG be the gate voltage swing that the MOSFET QG is rated to (often 10 V).
    1. TPS23754 TPS23754-1 TPS23756 il_eq8_lvs885.gif
    2. Compute gate drive power if VC is 12 V, QGATE is 17 nC, and QGAT2 is 8 nC.
      TPS23754 TPS23754-1 TPS23756 il_eq9_lvs885.gif
    3. TPS23754 TPS23754-1 TPS23756 il_eq10_lvs885.gif
      PDRIVE = 61.2 mW + 28.8 mW = 90 mW
    4. This illustrates why MOSFET QG should be an important consideration in selecting the switching MOSFETs.
  2. Estimate the required bias current at some intermediate voltage during the CVC discharge. For the TPS23754 device, 12 V provides a reasonable estimate. Add the operating bias current to the gate drive current.
    1. TPS23754 TPS23754-1 TPS23756 il_eq11_lvs885.gif
    2. ITOTAL = IDRIVE + IOPERATING = 7.5 mA + 0.92 mA = 8.42 mA
  3. Compute the required CVC based on start-up within the typical soft-start period of 4 ms.
    1. TPS23754 TPS23754-1 TPS23756 il_eq12_lvs885.gif
    2. For this case, a standard 10-μF electrolytic plus a 0.47 μF should be sufficient.
  4. Compute the initial time to start the converter when operating from PoE.
    1. Using a typical bootstrap current of 4 mA, compute the time to start-up.
    2. TPS23754 TPS23754-1 TPS23756 il_eq13_lvs885.gif
  5. Compute the fault duty cycle and hiccup frequency:
    1. TPS23754 TPS23754-1 TPS23756 il_eq14_lvs885.gif
    2. TPS23754 TPS23754-1 TPS23756 il_eq15_lvs885.gif
      1. The optocoupler current is 0 mA because the output is in current limit.
      2. Also, it is assumed IT2P is 0 mA.
    3. TPS23754 TPS23754-1 TPS23756 il_eq16_lvs885.gif
    4. TPS23754 TPS23754-1 TPS23756 il_eq17_lvs885.gif
  6. With the TPS23754 device, the voltage rating of CVC1 and CVC2 should be 25 V minimum while with the TPS23756 rating can be 16 V.