SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
COMMAND = 18h with 1 Data Byte, Write Only
Push button register.
Each bit corresponds to a particular cycle (detect or class restart) per port. Each cycle can be individually triggered by writing a 1 at that bit location, while writing a 0 does not change anything for that event.
In Manual mode, a single cycle (detect or class restart) will be triggered while in Semiauto mode, it sets the corresponding bit in the Detect/Class Enable register.
A Read operation will return 00h.
During tOVLD, tLIM or tSTART cool down cycle, any Detect/Class Restart command for that port will be accepted but the corresponding action will be delayed until end of cool-down period.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCL4 | RCL3 | RCL2 | RCL1 | RDET4 | RDET3 | RDET2 | RDET1 |
W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7–4 | RCL4–RCL1 | W | 0 | Restart classification bit |
3–0 | RDET4–RDET1 | W | 0 | Restart detection bits |