JAJSHI6G June   2018  – July 2021 TPS25830-Q1 , TPS25831-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO and Start-up
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short to Battery Protection
        1. 10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
        3. 10.3.11.3 CC IEC and OVP Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
        3. 10.3.16.3 Configuration Channel Pins CC1 and CC2
        4. 10.3.16.4 Current Capability Advertisement and VCONN Overload Protection
        5. 10.3.16.5 Plug Polarity Detection
      17. 10.3.17 Device Power Pins (IN, CSN/OUT, and PGND)
      18. 10.3.18 Thermal Shutdown
      19. 10.3.19 Power Wake
      20. 10.3.20 Thermal Sensing with NTC (TPS25831-Q1)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Standby Mode
      3. 10.4.3 Active Mode
      4. 10.4.4 Device Truth Table (TT)
      5. 10.4.5 USB Port Operating Modes
        1. 10.4.5.1 USB Type-C Mode
        2. 10.4.5.2 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        3. 10.4.5.3 Charging Downstream Port (CDP) Mode
        4. 10.4.5.4 Dedicated Charging Port (DCP) Mode (TPS25831-Q1 Only)
          1. 10.4.5.4.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.4.5.4.2 DCP Divider-Charging Scheme
          3. 10.4.5.4.3 DCP 1.2-V Charging Scheme
        5. 10.4.5.5 DCP Auto Mode (TPS25831-Q1 Only)
      6. 10.4.6 High-Bandwidth Data-Line Switches (TPS25830-Q1 only)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Undervoltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 LD_DET, POL, and FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Related Links
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 サポート・リソース
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Thermal Sensing with NTC (TPS25831-Q1)

The NTC input pin allows for user programmable thermal protection. See the Electrical Characteristics for NTC pin thresholds. The NTC input pin threshold is ratiometric with VCC. The external resistor divider setting VNTC must be connected to the TPS25831-Q1 VCC pin to achieve accurate results, see Figure 10-28 and Figure 10-29. When VNTC = 0.5 × VCC (approximately 2.5-V typically), the TPS25831-Q1 performs two actions:

  1. If operating with 3-A Type-C advertisement, the CC1 and CC2 pin automatically reduces advertisement to the 1.5-A level.
  2. The THERM_WARN flag is asserted to provide an indication of the over-temperature condition. FAULT is NOT asserted at this time.

GUID-7A5FC358-C38B-4EDD-A243-DF998CA09720-low.gifFigure 10-28 NTC Input Pin
GUID-60151290-9A9B-44AA-BAE6-1D3285C6C4AD-low.gifFigure 10-29 TPS25831-Q1 Behavior When Trigger NTC Threshold

If the overtemprature condition persists causing VNTC = VCC × 0.65 (3.25-V typical), the TPS25831-Q1 turns off the buck regulator and pulls the LS_GD pin low. The THERM_WARN flag remains asserted; however, the FAULT pin is NOT asserted for this condition.

Tuning the VNTC theshold levels of VWARN_HIGH and VSD_HIGH is achieved by adding RSER, RPARA, or both RSER and RPARA in conjunction with RNTC. Figure 10-30 is an example illustrating how to set the THERM_WARN threshold between 75°C and 90°C with a ΔT between THERM_WARN assertion and device shutdown of 17°C to 28°C. Consult the chosen NTC manufacturer's specification for the value of β. It may take some iteration to establish the desired warning and shutdown thresholds.

Below is NTC spec and resistor value used in Figure 10-30 example.

  • R0 = 470 kΩ. β = 4750. RNTC=R0 × exp β × (1/T-1/T0)
  • RPARA = 100 kΩ.
  • RSER = 5 kΩ.
  • RB = RNTC(at T_ THERM_WARN) = 32 kΩ

GUID-1221BCA3-A139-447C-8F7F-7668A844E78A-low.gifFigure 10-30 VNTC Threshold Examples

The NTC resistor should be placed near the hottest point on the PCB. In most cases, this will be close to the SW node of the TPS25831-Q1, near the buck inductor, RSNS sense resistor and external MOSFETs (if used).

GUID-1DB39BD8-A92F-4713-8110-261CF839EA24-low.gifFigure 10-31 NTC Placement Example