JAJSCZ7 February   2017 TPS3852-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 RESET
      2. 7.3.2 Manual Reset (MR)
      3. 7.3.3 Undervoltage Fault Detection
      4. 7.3.4 Watchdog Mode
        1. 7.3.4.1 SET1
        2. 7.3.4.2 Window Watchdog Timer
        3. 7.3.4.3 Watchdog Input (WDI)
        4. 7.3.4.4 CWD
        5. 7.3.4.5 Watchdog Output (WDO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR (VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD(min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CWD Functionality
        1. 8.1.1.1 Factory-Programmed Timing Options
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Overdrive Voltage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Monitoring the 3.3-V Rail
        2. 8.2.2.2 Calculating RESET and the WDO Pullup Resistor
        3. 8.2.2.3 Setting the Window Watchdog
        4. 8.2.2.4 Watchdog Disabled During Initialization Period
      3. 8.2.3 Glitch Immunity
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 評価モジュール
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DRB Package
8-Pin VSON
Top View

Pin Functions

NAME NO. I/O DESCRIPTION
CWD 2 — Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further enables the selection of the preset watchdog timeouts; see the Timing Requirements table.
When using a capacitor, the TPS3852-Q1 determines the window watchdog upper boundary with Equation 1.
See Table 4 and the CWD Functionality section for additional information.
GND 4 — Ground pin
MR 3 I Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD.
RESET remains low for a fixed reset delay (tRST) time after MR is deasserted (high).
RESET 8 O Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). RESET goes low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the RESET timeout counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the monitored voltage is within the correct operating range (above VITN + VHYST) and the RESET timeout is complete.
SET1 5 I Logic input. Grounding the SET1 pin disables the watchdog timer.
VDD 1 I Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
WDI 6 I Watchdog input. A falling transition (edge) must occur at this pin between the lower (tWDL(max)) and upper (tWDU(min)) window boundaries in order for WDO to not assert.
When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. The input at WDI is ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND.
WDO 7 O Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). WDO goes low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-impedance state.
Thermal pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.