VOLTAGE REFERENCE |
VFB |
FB input voltage |
TJ = 25°C, 3 V < VVDD < 20 V |
597 |
600 |
603 |
mV |
–20°C < TJ < 125°C, 3 V < VVDD < 20 V |
592 |
600 |
608 |
INPUT SUPPLY |
VVDD |
Input supply voltage range |
|
3 |
|
20 |
V |
IDDSD |
Shutdown supply current |
VEN/SS < 0.2 V |
|
70 |
100 |
µA |
IDDQ |
Quiescent, nonswitching |
Let EN/SS float, VFB = 1 V |
|
2.5 |
3.5 |
mA |
ENABLE/SOFT-START |
VIH |
High-level input voltage, EN/SS |
|
0.55 |
0.7 |
1 |
V |
VIL |
Low-level input voltage, EN/SS |
|
0.27 |
0.3 |
0.33 |
V |
ISS |
Soft-start source current |
|
8 |
10 |
12 |
µA |
VSS |
Soft-start voltage level |
|
0.4 |
0.8 |
1.3 |
V |
BP REGULATOR |
VBP |
Output voltage |
IBP = 10 mA |
6.2 |
6.5 |
6.8 |
V |
VDO |
Regulator dropout voltage, VVDD – VBP |
IBP = 25 mA, VVDD = 3 V |
|
70 |
110 |
mV |
OSCILLATOR |
fSW |
PWM frequency |
|
540 |
600 |
660 |
kHz |
VRAMP(1) |
Ramp amplitude |
|
VVDD/6.6 |
VVDD/6 |
VVDD/5.4 |
V |
fSWFSS |
Frequency spread-spectrum frequency deviation |
|
12% |
|
|
fSW |
fMOD |
Modulation frequency |
|
|
25 |
|
kHz |
PWM |
DMAX (1) |
Maximum duty cycle |
VFB = 0 V, 3 V < VVDD < 20 V |
90% |
|
|
|
tON(min)(1) |
Minimum controllable pulse width |
|
|
|
70 |
ns |
tDEAD |
Output driver dead time |
HDRV off to LDRV on |
5 |
25 |
35 |
ns |
LDRV off to HDRV on |
5 |
25 |
30 |
ERROR AMPLIFIER |
GBWP (1) |
Gain bandwidth product |
|
10 |
24 |
|
MHz |
AOL (1) |
Open loop gain |
|
60 |
|
|
dB |
IIB |
Input bias current (current out of FB pin) |
VFB = 0.6 V |
|
|
75 |
nA |
IEAOP |
Output source current |
VFB = 0 V |
2 |
|
|
mA |
IEAOM |
Output sink current |
VFB = 1 V |
2 |
|
|
PGOOD |
VOV |
Feedback upper voltage limit for PGOOD |
|
655 |
675 |
700 |
mV |
VUV |
Feedback lower voltage limit for PGOOD |
|
500 |
525 |
550 |
VPGD-HYST |
PGOOD hysteresis voltage at FB |
|
|
25 |
40 |
RPGD |
PGOOD pulldown resistance |
VFB = 0 V, IFB = 5 mA |
|
30 |
70 |
Ω |
IPGDLK |
PGOOD leakage current |
550 mV < VFB < 655 mV, VPGOOD = 5 V |
|
10 |
20 |
µA |
OUTPUT DRIVERS |
RHDHI |
High-side driver pullup resistance |
VBOOT – VSW = 5 V, IHDRV = –100 mA |
0.8 |
1.5 |
2.5 |
Ω |
RHDLO |
High-side driver pulldown resistance |
VBOOT – VSW = 5 V, IHDRV = 100 mA |
0.5 |
1 |
2.2 |
Ω |
RLDHI |
Low-side driver pullup resistance |
ILDRV = -100 mA |
0.8 |
1.5 |
2.5 |
Ω |
RLDLO |
Low-side driver pulldown resistance |
ILDRV = 100 mA |
0.35 |
0.6 |
1.2 |
Ω |
tHRISE (1) |
High-side driver rise time |
CLOAD = 5 nF |
|
15 |
|
ns |
tHFALL(1) |
High-side driver fall time |
|
|
12 |
|
ns |
tLRISE(1) |
Low-side driver rise time |
|
|
15 |
|
ns |
tLFALL(1) |
Low-side driver fall time |
|
|
10 |
|
ns |
OVERCURRENT PROTECTION |
tPSSC(min)(1) |
Minimum pulse time during short circuit |
|
|
250 |
|
ns |
tBLNKH(1) |
Switch leading-edge blanking pulse time |
|
|
150 |
|
ns |
VOCH |
OC threshold for high-side FET |
TJ = 25°C |
360 |
450 |
580 |
mV |
IOCSET |
OCSET current source |
TJ = 25°C |
9.5 |
10 |
10.5 |
µA |
VLD-CLAMP |
Maximum clamp voltage at LDRV |
|
260 |
340 |
400 |
mV |
VOCLOS |
OC comparator offset voltage for low-side FET |
TJ = 25°C |
–8 |
|
8 |
mV |
VOCLPRO(1) |
Programmable OC range for low-side FET |
TJ = 25°C |
12 |
|
300 |
mV |
VTHTC(1) |
OC threshold temperature coefficient (both high-side and low-side) |
|
|
3000 |
|
ppm |
tOFF |
OC retry cycles on EN/SS pin |
|
|
4 |
|
Cycle |
BOOT DIODE |
VDFWD |
Bootstrap diode forward voltage |
IBOOT = 5 mA |
|
0.8 |
|
V |
THERMAL SHUTDOWN |
TJSD(1) |
Junction shutdown temperature |
|
|
145 |
|
°C |
TJSDH(1) |
Hysteresis |
|
|
20 |
|
°C |