SLVSAR7E June   2011  – October 2016 TPS43350-Q1 , TPS43351-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.3.1.1 Frequency Selection and External Synchronization
        2. 7.3.1.2 Enable Inputs
        3. 7.3.1.3 Feedback Inputs
        4. 7.3.1.4 Soft-Start Inputs
        5. 7.3.1.5 Current-Mode Operation
        6. 7.3.1.6 Current Sensing and Current Limit With Foldback
        7. 7.3.1.7 Slope Compensation
        8. 7.3.1.8 Power-Good Outputs and Filter Delays
        9. 7.3.1.9 Light-Load PFM Mode
      2. 7.3.2 Frequency-Hopping Spread Spectrum (TPS43351-Q1 Only)
      3. 7.3.3 Gate-Driver Supply (VREG, EXTSUP)
      4. 7.3.4 External P-Channel Drive (GC2) and Reverse-Battery Protection
      5. 7.3.5 Undervoltage Lockout and Overvoltage Protection
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  BuckA Component Selection
          1. 8.2.2.1.1 Minimum ON Time, tON min
          2. 8.2.2.1.2 Current-Sense Resistor RSENSE
        2. 8.2.2.2  Inductor Selection L
        3. 8.2.2.3  Inductor Ripple Current IRIPPLE
        4. 8.2.2.4  Output Capacitor COUTA
        5. 8.2.2.5  Bandwidth of Buck Converter fC
        6. 8.2.2.6  Selection of Components for Type II Compensation
        7. 8.2.2.7  Resistor Divider Selection for Setting VOUTA Voltage
        8. 8.2.2.8  BuckB Component Selection
        9. 8.2.2.9  Resistor Divider Selection for Setting VOUT Voltage
        10. 8.2.2.10 BUCKx High-Side and Low-Side N-Channel MOSFETs
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Buck Converter
      2. 10.1.2 Other Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Detailed Description

Overview

The TPS43350-Q1 and TPS43351-Q1 devices feature two current-mode synchronous buck controllers. With light loads, the buck controllers can be enabled to automatically operate in low-power mode, consuming just 30 µA of quiescent current. The buck controllers have independent soft-start capability and power-good indicators. Current foldback in the buck controllers provide external MOSFET protection. The switching frequency is programmable over 150 kHz to 600 kHz or can be synchronized to an external clock in the same range. Additionally, the TPS43351-Q1 offers frequency-hopping spread-spectrum operation.

Functional Block Diagram

TPS43350-Q1 TPS43351-Q1 blk_dia_SLVSAR7.gif

Feature Description

Buck Controllers: Normal Mode PWM Operation

Frequency Selection and External Synchronization

The buck controllers operate using constant-frequency peak-current mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching frequency to 400 kHz. Using a resistor at RT, one can set another frequency according to Equation 1.

Equation 1. TPS43350-Q1 TPS43351-Q1 eq20_lvsa82.gif

For example:

  • 600 kHz requires 40 kΩ
  • 150 kHz requires 160 kΩ

It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the specified range. The device can also detect a loss of clock at this pin, and on detection of this condition, the device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies, 180 degrees out of phase.

Enable Inputs

Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins, with a threshold of 1.7 V for the high level, and with direct connection to the battery permissible for self-bias. The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on these pins enables the respective buck controllers. But with both buck controllers disabled, the device shuts down and consumes a current less than 4 µA.

Feedback Inputs

The right resistor feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup current source as a protection feature in case the pins open up as a result of physical damage.

Soft-Start Inputs

In order to avoid large inrush currents, the buck controllers have independent programmable soft-start timers. The voltage at the SSx pins acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V, which then becomes the reference for the buck controllers. Use Equation 2 to calculate the soft-start ramp time..

Equation 2. TPS43350-Q1 TPS43351-Q1 eq62_lvsa82.gif

where

  • ISS = 1 µA (typical)
  • ∆V = 0.8 V
  • CSS is the required capacitor for ∆t, the desired soft-start time.

An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be tracked via a suitable resistor-divider network.

Current-Mode Operation

Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as a target for the peak inductor current. The device senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. This process maintains the output voltage in regulation.

The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck regulator switches at one-fourth of its normal frequency.

Current Sensing and Current Limit With Foldback

Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-direction current limit).

Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the COMPx node drops low. A clamp is on its lower end as well, in order to limit the maximum current in the low-side MOSFET (reverse-direction current limit).

An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input), 50 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics provide a guide for using the correct current-limit sense voltage.

The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range. This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 11 shows DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.

TPS43350-Q1 TPS43351-Q1 dcr_sensing_config_lvsar7.gif Figure 11. DCR Sensing Configuration

Slope Compensation

Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor according to Equation 3.

Equation 3. TPS43350-Q1 TPS43351-Q1 eq01_lvsa82.gif

where

  • L is the buck regulator inductor in henries.
  • RS is the sense resistor in ohms.
  • fsw is the buck-regulator switching frequency in hertz.

Power-Good Outputs and Filter Delays

Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-drain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow through the resistor when the buck controller is in the powered-down state.

In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to its set value after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after the same delay. Use of this delay can pauses the delay of the reset. Program the duration of the delay of by using a suitable capacitor at the DLYAB pin according to Equation 4.

Equation 4. TPS43350-Q1 TPS43351-Q1 eq99_lvsa82.gif

When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay timing is common to both the buck rails, but the power-good comparators and indicators function independently.

Light-Load PFM Mode

An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.

In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have been chosen appropriately as recommended in the Slope Compensation section.

In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference. Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely proportional to the difference – Sx2. At the end of this on-time, the high-side MOSFET turns off and the current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and 35 µA when both channels are active.

As the load increases, the pulses become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher than 80% duty cycle of the high-side MOSFET.

The TPS43350-Q1 and TPS43351-Q1 can support the full current load during low-power mode until the transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10% (typical) of full-load current if the selection of inductor and sense resistor is as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.

In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for low-power-mode entry.

Frequency-Hopping Spread Spectrum (TPS43351-Q1 Only)

The TPS43351-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this device, whenever the SYNC pin is high, the internal oscillator frequency varies from one cycle to the next within a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a linear feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift register is long enough to make the hops pseudo-random in nature and is designed in such a way that the frequency shifts only by one step at each cycle to avoid large jumps in the buck switching frequencies.

Table 1. Frequency Hopping Control

SYNC
TERMINAL
FREQUENCY SPREAD SPECTRUM (FSS) COMMENTS
External clock Not active Device in forced continuous mode, internal PLL locks into external clock between 150 kHz and 600 kHz.
Low or open Not active Device can enter discontinuous mode. Automatic LPM entry and exit, depending on load conditions
High TPS43350-Q1: FSS not active Device in forced continuous mode
TPS43351-Q1: FSS active

Gate-Driver Supply (VREG, EXTSUP)

The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output (5.8 V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 µF to 10 µF. This pin has internal current-limit protection; do not use it to power any other circuits.

VIN powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical). In case VIN expected to go to high levels, there can be excessive power dissipation in this regulator, especially at high switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin, which can be connected to a supply lower than VIN but high enough to provide the gate drive. When the voltage on EXTSUP is greater than 4.6 V, the linear regulator automatically switches to EXTSUP as its input, to provide this advantage. Efficiency improvements are possible when using one of the switching regulator rails from the TPS4335x-Q1 or any other voltage available in the system to power EXTSUP. The maximum voltage for application to EXTSUP is 9 V.

TPS43350-Q1 TPS43351-Q1 intgatedrvsupp_lvsb16.gif Figure 12. Internal Gate-Driver Supply

Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as it provides a large gate drive and hence better on-resistance of the external MOSFETs. When using EXTSUP, always keep the buck rail supplying EXTSUP enabled. Alternatively, if it is necessary to switch off the buck rail supplying EXTSUP, place a diode between the buck rail and EXTSUP. During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.

External P-Channel Drive (GC2) and Reverse-Battery Protection

The TPS4335x-Q1 includes a gate driver for an external P-channel MOSFET which can be connected across the reverse-battery diode. This is useful to reduce power losses and the voltage drop over a typical diode. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET.

TPS43350-Q1 TPS43351-Q1 rev_bat_prot_lvsar7.gif Figure 13. Reverse-Battery Protection Option

Undervoltage Lockout and Overvoltage Protection

The TPS4335x-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout disables the device. Note: if VIN drops, VREG drops as well; hence, the gate-drive voltage decreases, whereas the digital logic is fully functional. A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent transient spikes from shutting down the device, under- and overvoltage protection have filter times of 5 µs (typical).

When the voltages return to the normal operating region, the enabled switching regulators startwith a new soft-start ramp for the buck regulators.

Thermal Protection

The TPS4335x-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die temperature exceeds the thermal shutdown threshold of 165ºC due to excessive power dissipation (for example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers turn off. Then restart when the temperature has fallen by 15ºC.

Device Functional Modes

Table 2 lists the modes of operation for the device.

Table 2. Mode of Operation

ENABLE AND INHIBIT PINS BUCK CONTROLLER STATUS DEVICE STATUS QUIESCENT CURRENT
ENA ENB SYNC
Low Low X Shutdown Shutdown Approximately 4 µA
Low High Low BuckB running BuckB: LPM enabled Approximately 30 µA (light loads)
High BuckB: LPM inhibited mA range
High Low Low BuckA running BuckA: LPM enabled Approximately 30 µA (light loads)
High BuckA: LPM inhibited mA range
High High Low BuckA and BuckB running BuckA and BuckB: LPM enabled Approximately 35 µA (light loads)
High BuckA and BuckB: LPM inhibited mA range