SLVS616C November   2005  – December 2014 TPS51124

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  Light-Load Condition
      3. 7.3.3  Low-Side Driver
      4. 7.3.4  High-Side Driver
      5. 7.3.5  PWM Frequency and Adaptive On-Time Control
      6. 7.3.6  Powergood
      7. 7.3.7  Output Discharge Control
      8. 7.3.8  Current Protection
      9. 7.3.9  Over and Undervoltage Protection
      10. 7.3.10 UVLO Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Soft-Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

10 Layout

10.1 Layout Guidelines

Certain points must be considered before starting a layout using the TPS51124.

  • Connect RC low-pass filter from V5IN to V5FILT, 1-μF and 3.3-Ω are recommended. Place the filter capacitor close to the IC, within 12 mm (0.5 inch) if possible.
  • Connect the over-current setting resistors from TRIPx to GND, and as close as possible to the IC. The trace from TRIPx to resistor, and resistor to GND, should avoid coupling to high-voltage switching node.
  • The discharge path (VOx) should have a dedicated trace to the output capacitor(s), separate from the output voltage sensing trace. Use 1,5-mm (60 mils) or wider trace, with no loops. Tie the feedback-current-setting resistor (the resistor between VFBx to GND) close to the IC’s GND. The trace from this resistor to VFBx pin should be short and thin. Place on the component side and avoid vias between this resistor and the IC.
  • Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0,65-mm (25 mils) or wider trace.
  • All sensitive analog traces and components such as VOx, VFBx, GND, ENx, PGOODx, TRIPx, V5FILT, and TONSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx, DRVHx, or VBSTx nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components.
  • Gather ground terminal of VIN capacitor(s), Vout capacitor(s), and source of low-side MOSFETs as close as possible. GND (signal ground) and PGNDx (power ground) should be connected strongly together near the IC. PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
  • In order to effectively remove heat from the package, prepare thermal land and solder to the package’s thermal pad. Two by two or more vias with a 0,33-mm (13 mils) diameter connected from the thermal land to the internal ground plane should be used to help dissipation. Do NOT connect PGNDx to this thermal land underneath the package.

10.2 Layout Example

layout_51124.gifFigure 26. Layout Example