SLVSCF8 July   2014 TPS54060-EP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Low-Dropout Operation and Bootstrap Voltage (Boot)
      4. 8.3.4  Error Amplifier
      5. 8.3.5  Voltage Reference
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting UVLO
      8. 8.3.8  Slow Start/Tracking Pin (SS/TR)
      9. 8.3.9  Overload Recovery Circuit
      10. 8.3.10 Sequencing
      11. 8.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      12. 8.3.12 Overcurrent Protection and Frequency Shift
      13. 8.3.13 Selecting the Switching Frequency
      14. 8.3.14 How to Interface to RT/CLK Pin
      15. 8.3.15 Power Good (PWRGD Pin)
      16. 8.3.16 Overvoltage Transient Protection (OVTP)
      17. 8.3.17 Thermal Shutdown
      18. 8.3.18 Small Signal Model for Loop Response
      19. 8.3.19 Simple Small Signal Model for Peak Current Mode Control
      20. 8.3.20 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Skip Eco-Mode
      2. 8.4.2 DCM and Eco-Mode Boundary
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Selecting the Switching Frequency
        2. 9.2.2.2  Output Inductor Selection (LO)
        3. 9.2.2.3  Output Capacitor
        4. 9.2.2.4  Catch Diode
        5. 9.2.2.5  Input Capacitor
        6. 9.2.2.6  Slow Start Capacitor
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  UVLO Set Point
        9. 9.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 9.2.2.10 Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Dissipation Estimate
    2. 10.2 Power Supply Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Estimated Circuit Area
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

10.1 Power Dissipation Estimate

The following formulas show how to estimate the IC power dissipation under CCM operation. Do not use these equations if the device is working in DCM.

The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd), and supply current (Pq).

Equation 49. eq56_lvs795.gif
Equation 50. eq57_lvs795.gif
Equation 51. eq58_lvs795.gif
Equation 52. eq59_lvs795.gif

where:

  • IOUT is the output current (A).
  • RDS(on) is the on-resistance of the high-side MOSFET (Ω).
  • VOUT is the output voltage (V).
  • VIN is the input voltage (V).
  • ƒsw is the switching frequency (Hz).

So

Equation 53. eq60_lvs795.gif

For given TA,

Equation 54. eq61_lvs795.gif

For given TJMAX = 150°C

Equation 55. eq62_lvs795.gif

where

  • Ptot is the total device power dissipation (W).
  • TA is the ambient temperature (°C).
  • TJ is the junction temperature (°C).
  • Rth is the thermal resistance of the package (°C/W).
  • TJMAX is maximum junction temperature (°C).
  • TAMAX is maximum ambient temperature (°C).

There will be additional power losses in the regulator circuit due to the inductor AC and DC losses, catch diode, and trace resistance that will impact the overall efficiency of the regulator.

10.2 Power Supply Considerations

TPS2105-EP requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. Ceramic capacitors lose capacitance when a DC bias is applied across the capacitor. This capacitance loss is due to the polarization of the ceramic material. The capacitance loss is not permanent; after a large DC bias is applied, reducing the DC bias reduces the degree of polarization and capacitance increases. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases.

All tantalum capacitors have Tantalum (Ta) particles sintered together to form an anode. The cathode material can either be the traditional MnO2 or a conductive polymer. Because MnO2 is actually a semiconductor, it has a very-high amount of resistance associated with it. A characteristic of this material is that as temperature changes so does its conductivity. So MnO2-based Tantalum capacitors have relatively high ESR and that ESR shifts significantly across the operational temperature range.

However, polymer-based cathodes use a highly-conductive polymer material. Because the material is inherently conductive, Tantalum-polymers have a relatively low ESR compared to their MnO2 counterparts in the same voltage and capacitance ranges.

All Tantalum capacitors have a voltage derating factor associated with them. Because the Polymer material puts less stress on the Tantalum-Pentoxide dielectric during reflow soldering, more voltage can be applied compared to a MnO2-based Tantalum. For polymer-based capacitors, TI recommends 20% derating whereas the MnO2-based tantalum capacitors require 50% or higher derating. Refer to the capacitor vendor data sheet for more details regarding the derating guidelines.