JAJSCY5A December   2016  – January 2017 TPS54260-EP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode Control Scheme
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (Boot)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting the Output Voltage
      8. 7.3.8  Enable and Adjusting Undervoltage Lockout (UVLO)
      9. 7.3.9  Slow-Start and Tracking Pin (SS/TR)
      10. 7.3.10 Overload Recovery Circuit
      11. 7.3.11 Constant Switching Frequency and Timing Resistor (RT and CLK Pin)
      12. 7.3.12 Overcurrent Protection and Frequency Shift
      13. 7.3.13 Selecting the Switching Frequency
      14. 7.3.14 How to Interface to RT/CLK Pin
      15. 7.3.15 Power Good (PWRGDPin)
      16. 7.3.16 Overvoltage Transient Protection (OVTP)
      17. 7.3.17 Thermal Shutdown
      18. 7.3.18 Small Signal Model for Loop Response
      19. 7.3.19 Simple Small-Signal Model for Peak Current Mode Control
      20. 7.3.20 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sequencing
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting The Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  UVLO Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 Discontinuous Mode and Eco-mode Control Scheme Boundary
        12. 8.2.2.12 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Estimated Circuit Area
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted).(1)
MIN MAX UNIT
Input voltage VIN –0.3 65 V
EN(2) –0.3 5
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-PH –0.3 8 V
PH –0.6 65
200 ns –1 65
30 ns –2 65
Maximum dc voltage, T J= –40°C –0.85
Voltage difference PAD to GND ±200 mV
Source current EN 100 μA
BOOT 100 mA
VSENSE 10 μA
PH Current limit
RT/CLK 100 μA
Sink current VIN Current limit
COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –55 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TJ Operating junction temperature –55 150 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS54260-EP UNIT
DRC (VSON) DGQ (HVSSOP)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance Standard board 40 62.5 °C/W
Custom board(3) — 57
RθJC(top) Junction-to-case (top) thermal resistance 65 83 °C/W
RθJB Junction-to-board thermal resistance 8 28 °C/W
ψJT Junction-to-top characterization parameter 0.6 1.7 °C/W
ψJB Junction-to-board characterization parameter 7.5 20.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.8 21 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
(3) Test boards conditions:
  1. 3 in × 3 in, 2 layers, thickness: 0.062 in.
  2. 2-oz copper traces located on the top of the PCB.
  3. 2-oz copper ground plane, bottom layer.
  4. 6-thermal vias (13 mil) located under the device package.

6.5 Electrical Characteristics

TJ = –55 to 150°C, VIN = 3.5 to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 60 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 3.5 V ≤ VIN ≤ 60 V 1.3 10 μA
Operating: nonswitching supply current VSENSE = 0.83 V, VIN = 12 V 138 200 μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.14 1.25 1.36 V
Input current Enable threshold +50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
Voltage reference TJ = 25°C 0.792 0.8 0.808 V
0.78 0.8 0.82
HIGH-SIDE MOSFET
on resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 310 μS
Error amplifier transconductance (gM) during slow-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 70 μS
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±27 μA
COMP to switch current transconductance 10.5 A/V
CURRENT LIMIT
Current limit threshold VIN = 12 V 3.5 6.1 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 581 720 kHz
Switching frequency range using CLK mode 300 2200 kHz
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW-START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.15 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 382 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
VVSENSE VSENSE threshold VSENSE falling 92%
VSENSE rising 94%
VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA 0.95 1.9 V

6.6 Typical Characteristics

TPS54260-EP D001_SLVSDN9.gif
Figure 1. On Resistance vs Junction Temperature
TPS54260-EP D003_SLVSDN9.gif
VI = 12 V
Figure 3. Switch Current Limit vs Junction Temperature
TPS54260-EP C005_SLVS919.gif
Figure 5. Switching Frequency vs RT/CLK Resistance High Frequency Range
TPS54260-EP D007_SLVSDN9.gif
VI = 12 V
Figure 7. EA Transconductance During Slow-Start vs Junction Temperature
TPS54260-EP D009_SLVSDN9.gif
Figure 9. SS/TR Charge Current vs Junction Temperature
TPS54260-EP C014_SLVS919.gif
Figure 11. Switching Frequency vs VSENSE
TPS54260-EP icc_vi_slvsdn9.gif
TJ = 25°C
Figure 13. Shutdown Supply Current vs Input Voltage (VIN)
TPS54260-EP icc_vi2_slvsdn9.gif
TJ = 25°C VI(VSENSE) = 0.83 V
Figure 15. VIN Supply Current vs Input Voltage
TPS54260-EP D017_SLVSDN9.gif
Figure 17. PWRGD Threshold vs Junction Temperature
TPS54260-EP offset_vs_slvsdn9.gif
TJ = 25°C VI = 12 V
Figure 19. SS/TR to VSENSE Offset vs VSENSE
TPS54260-EP D002_SLVSDN9.gif
Figure 2. Voltage Reference vs Junction Temperature
TPS54260-EP D004_SLVSDN9.gif
Figure 4. Switching Frequency vs Junction Temperature
TPS54260-EP C006_SLVS919.gif
Figure 6. Switching Frequency vs RT/CLK Resistance Low Frequency Range
TPS54260-EP D008_SLVSDN9.gif
VI = 12 V
Figure 8. EA Transconductance vs Junction Temperature
TPS54260-EP D010_SLVSDN9.gif
VI = 12 V
Figure 10. SS/TR Discharge Current vs Junction Temperature
TPS54260-EP D012_SLVSDN9.gif
Figure 12. Shutdown Supply Current vs Junction Temperature
TPS54260-EP D014_SLVSDN9.gif
VI = 12 V VI(VSENSE) = 0.83 V
Figure 14. VIN Supply Current vs Junction Temperature
TPS54260-EP D016_SLVSDN9.gif
Figure 16. PWRGD On Resistance vs Junction Temperature
TPS54260-EP D018_SLVSDN9.gif
Figure 18. Boot-PH UVLO vs Junction Temperature
TPS54260-EP D020_SLVSDN9.gif
VI = 12 V V(SS/TR) = 0.4 V
Figure 20. SS/TR to VSENSE Offset vs Temperature