SLVSC61A November   2013  – October 2016 TPS54341

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Low Dropout Operation and Bootstrap Voltage (BOOT)
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Enable and Adjusting Undervoltage Lockout
      7. 7.3.7  Soft-Start/Tracking Pin (SS/TR)
      8. 7.3.8  Sequencing
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
      11. 7.3.11 Synchronization to RT/CLK Pin
      12. 7.3.12 Power Good (PWRGD Pin)
      13. 7.3.13 Overvoltage Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 Small-Signal Model for Loop Response
      16. 7.3.16 Simple Small-Signal Model for Peak-Current-Mode Control
      17. 7.3.17 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Skip Eco-mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 Discontinuous Conduction Mode and Eco-mode Boundary
        12. 8.2.2.12 Estimated Circuit Area
        13. 8.2.2.13 Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TPS54341 is a 42 V, 3.5 A, step down regulator with an integrated high side MOSFET. Ideal applications are: 12 V, 24 V Industrial, Automotive and Communications Power Systems.

Typical Application

TPS54341 appsch_slvsc61.gif Figure 46. 3.3-V Output TPS54341 Design Example

Design Requirements

This section illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few parameters must be known in order to start the design process. These requirements are typically determined at the system level. The necessary calculations can be done using WEBENCH or the excel spreadsheet (SLVC452) located on the product. This design starts with the parameters in Table 1.

Table 1. Design Parameters

PARAMETER VALUE
Output voltage 3.3 V
Transient response 0.875 A to 2.625 A load step ΔVOUT = 4%
Maximum output current 3.5 A
Input voltage 12 V nominal 6 V to 42 V
Output voltage ripple 0.5% of VOUT
Start input voltage (rising VIN) 5.75 V
Stop input voltage (falling VIN) 4.5 V

Detailed Design Procedure

Selecting the Switching Frequency

The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest switching frequency possible because this produces the smallest solution size. High switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage and the frequency-foldback protection.

Equation 12 and Equation 13 must be used to calculate the upper limit of the switching frequency for the regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit.

The typical minimum on time, tonmin, is 135 ns for the TPS54341 device. For this example, the output voltage is 3.3 V and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to avoid pulse skipping from Equation 12. To ensure overcurrent runaway is not a concern during short circuits use Equation 13 to determine the maximum switching frequency for frequency foldback protection. With a maximum input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 mΩ, switch resistance of 87 mΩ, a current-limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 1260 kHz.

For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated maximums. To determine the timing resistance for a given switching frequency, use Equation 10 or the curve in Figure 6. The switching frequency is set by resistor R3 shown in Figure 46. For 600 kHz operation, the closest standard value resistor is 162 kΩ.

Equation 28. TPS54341 q_6a_values_slvsc61.gif
Equation 29. TPS54341 q_7a_values_slvsc61.gif
Equation 30. TPS54341 q_4a_values_lvsbb4.gif

Output Inductor Selection (LO)

To calculate the minimum value of the output inductor, use Equation 31.

KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer, however, the following guidelines may be used.

For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable. When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple current. This provides sufficienct ripple current with the input voltage at the minimum.

For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 4.8 μH. The nearest standard value is 5.6 μH. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 33 and Equation 34. For this design, the RMS inductor current is 3.5 A and the peak inductor current is 3.95 A. The chosen inductor is a WE 7443552560, which has a saturation current rating of 7.5 A and an RMS current rating of 6.7 A.

As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the TPS54341 device which is nominally 5.5 A.

Equation 31. TPS54341 q_lomin_slvsc61.gif
Equation 32. TPS54341 q_iripple_slvsc61.gif
Equation 33. TPS54341 q_ilrms_slvsc61.gif
Equation 34. TPS54341 q_ilpeak_lvsbK0.gif

Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the increased load current until the regulator responds to the load step. The regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for two clock cycles to maintain the output voltage within the specified range. Equation 35 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in VOUT for a load step from 0.875 A to 2.625 A. Therefore, ΔIOUT is 2.625 A – 0.875 A = 1.75 A and ΔVOUT = 0.04 × 3.3 = 0.13 V. Using these numbers gives a minimum capacitance of 44.9 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.

The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is shown in Figure 49. The excess energy absorbed in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the peak output voltage, and VI is the initial voltage. For this example, the worst case load step will be from 2.625 A to 0.875 A. The output voltage increases during this load transition and the stated maximum in our specification is 4 % of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. VI is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 36 yields a minimum capacitance of 38.6 μF.

Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the inductor ripple current. Equation 37 yields 11.4 μF.

Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 38 indicates the ESR should be less than 18 mΩ.

The most stringent criteria for the output capacitor is 44.9 μF required to maintain the output voltage within regulation tolerance during a load transient.

Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, a 100-μF ceramic capacitor with 5 mΩ of ESR is used. The derated capacitance is 70 µF, well above the minimum required capacitance of 44.9 µF.

Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 39 can be used to calculate the RMS ripple current that the output capacitor must support. For this example, Equation 39 yields 261 mA.

Equation 35. TPS54341 q_cout1_lvsBK0.gif
Equation 36. TPS54341 q_cout2_lvsBK0.gif
Equation 37. TPS54341 q_cout3_lvsBK0.gif
Equation 38. TPS54341 q_Resr_lvsBK0.gif
Equation 39. TPS54341 q_icoutrms_lvsBK0.gif

Catch Diode

The TPS54341 device requires an external catch diode between the SW pin and GND. The selected diode must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of 42 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54341 device.

For the example design, the PDS560 Schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the PDS560 is 0.55 V at 3.5 A.

The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 40 is used to calculate the total power dissipation, including conduction losses and AC losses of the diode.

The PDS560 diode has a junction capacitance of 90 pF at 42 V input voltage. Using Equation 40, the total loss in the diode is 2.27 W.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop.

Equation 40. TPS54341 q_pd_slvsc61.gif

Input Capacitor

The TPS54341 device requires a high-quality ceramic-type X5R or X7R input-decoupling capacitor with at least 3 μF of effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54341 device. The input ripple current can be calculated using Equation 41.

The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 42 V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, or 100 V. For this example, two 2.2-μF 100-V capacitors in parallel are used. Table 2 shows several choices of high voltage capacitors.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 41. Using the design example values, IOUT = 3.5 A, CIN = 4.4 μF, ƒSW = 600 kHz, yields an input voltage ripple of 331 mV and a rms input ripple current of 1.74 A as seen in Equation 42.

Equation 41. TPS54341 q_Ic_rms_lvsBK0.gif
Equation 42. TPS54341 q_deltavin_lvsbb4.gif

Table 2. Capacitor Types

VENDOR VALUE (μF) EIA SIZE VOLTAGE (V) DIALECTRIC COMMENTS
Murata 1 to 2.2 1210 100 X7R GRM32 series
1 to 4.7 50
1 1206 100 GRM31 series
1 to 2.2 50
Vishay 1 to 1.8 2220 50 VJ X7R series
1 to 1.2 100
1 to 3.9 2225 50
1 to 1.8 100
TDK 1 to 2.2 1812 100 C series C4532
1.5 to 6.8 50
1 to 2.2 1210 100 C series C3225
1 to 3.3 50
AVX 1 to 4.7 1210 50 X7R dielectric series
1 100
1 to 4.7 1812 50
1 to 2.2 100

Slow-Start Capacitor

The slow-start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54341 device reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 43 can be used to find the minimum slow-start time, TSS, necessary to charge the output capacitor, COUT, from 10% to 90% of the output voltage, VOUT, with an average slow-start current of ISSavg. In the example, to charge the effective output capacitance of 70 µF up to 3.3 V with an average current of 1 A requires a 0.2-ms slow-start time.

Once the slow-start time is known, the slow-start capacitor value can be calculated using Equation 43. For the example circuit, the slow-start time is not too critical because the output capacitor value is 100 μF which does not require much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary value of 3.5 ms which requires a 9.3-nF slow-start capacitor calculated by Equation 44. For this design, the next larger standard value of 10 nF is used.

Equation 43. TPS54341 eq42_slvsc61.gif
Equation 44. TPS54341 eq6_slvsc61.gif

Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor must have a 10 V or higher voltage rating.

Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54341 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it should continue to do so until the input voltage falls below 4.5 V (UVLO stop).

Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For the example application, a 365 kΩ between Vin and EN (RUVLO1) and a 88.7 kΩ between EN and ground (RUVLO2) are required to produce the 8-V and 6.25-V start and stop voltages as seen in Equation 45 and Equation 46.

Equation 45. TPS54341 q_R1_lvsBK0.gif
Equation 46. TPS54341 q_R2_lvsBK0.gif

Output Voltage and Feedback Resistors Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6. Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but may also introduce noise immunity problems (see Equation 47).

Equation 47. TPS54341 q_Rhs_Rls_lvsBK0.gif

Compensation

There are several methods to design compensation for DC-DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least ten-times greater the modulator pole.

To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 48 and Equation 49. For COUT, use a derated value of 70 μF. Use equations Equation 50 and Equation 51 to estimate a starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 2411 Hz and ƒz(mod) is 455 kHz. Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of modulator pole and the switching frequency. Equation 50 yields 33.1 kHz and Equation 51 gives 26.9 kHz. Use the lower value of Equation 50 or Equation 51 for an initial crossover frequency. For this example, the target ƒco is 26.9 kHz.

Next, the compensation components are calculated with Equation 48 through Equation 51. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

Equation 48. TPS54341 q_fpmod_lvsBK0.gif
Equation 49. TPS54341 q_fzmod_lvsBK0.gif
Equation 50. TPS54341 q_fco_48khz_lvsBK0.gif
Equation 51. TPS54341 q_fco_25khz_lvsBK0.gif

To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance, gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5 V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 11.6 kΩ and a standard value of 11.5 kΩ is selected. Use Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields 5740 pF for compensating capacitor C5. 5600 pF is used for this design.

Equation 52. TPS54341 q_R4_slvsc61.gif
Equation 53. TPS54341 q_C5_lvsBK0.gif

A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the compensation pole. The selected value of C8 is 47 pF for this design example.

Equation 54. TPS54341 q_C8_lvsBK0.gif
Equation 55. TPS54341 q_C8_1overR4_slvsc61.gif

Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current is less than 340 mA. The power supply enters Eco-mode when the output current is lower than 30 mA. The input current draw is 260 μA with no load.

Estimated Circuit Area

Boxing in the components in the design of Figure 46 the estimated printed circuit board area is 1.025 in2 (661 mm2). This area does not include test points or connectors.

TPS54341 sch_slvsc61.gif Figure 47. TPS54341 Inverting Power Supply Based on the Application Note, SLVA317
TPS54341 split_rail_slvsc61.gif Figure 48. TPS54341 Split Rail Power Supply Based on the Application Note, SLVA369

Power Dissipation Estimate

The following formulas show how to estimate the TPS54341 power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is operating in discontinuous conduction mode (DCM).

The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and supply current (PQ). Example calculations are shown in Equation 56 through Equation 59 with the 12 V typical input voltage of the design example.

Equation 56. TPS54341 q_pcond_slvsc61.gif
Equation 57. TPS54341 q_psw_lvsb44.gif
Equation 58. TPS54341 q_pgd_lvsb44.gif
Equation 59. TPS54341 q_pq_lvsb44.gif

where

  • IOUT is the output current (A)
  • RDS(on) is the on-resistance of the high-side MOSFET (Ω)
  • VOUT is the output voltage (V)
  • VIN is the input voltage (V)
  • ƒSW is the switching frequency (Hz)
  • trise is the SW pin voltage rise time and can be estimated by trise = VIN × 0.16 ns/V + 3 ns
  • QG is the total gate charge of the internal MOSFET
  • IQ is the operating nonswitching supply current

Therefore, use Equation 60.

Equation 60. TPS54341 q_ptot_lvsBK0.gif

For given TA, use Equation 61.

Equation 61. TPS54341 q_tj_lvs795.gif

For given TJ(MAX) = 150°C, use Equation 62.

Equation 62. TPS54341 q_tamax_lvs795.gif

where

  • PTOT is the total device power dissipation (W)
  • TA is the ambient temperature (°C)
  • TJ is the junction temperature (°C)
  • RTH is the thermal resistance (°C/W)
  • TJ(MAX) is maximum junction temperature (°C)
  • TA(MAX) is maximum ambient temperature (°C)

There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and PCB trace resistance impacting the overall efficiency of the regulator.

Application Curves

TPS54341 ac_G001_lvsBK0.gif Figure 49. Load Transient
TPS54341 ac_G003_lvsBK0.gif
Figure 51. Startup With VIN
TPS54341 ac_G005_lvsBK0.gif Figure 53. Output Ripple CCM
TPS54341 ac_G007_lvsBK0.gif Figure 55. Output Ripple PSM
TPS54341 ac_G009_lvsBK0.gif Figure 57. Input Ripple DCM
TPS54341 G022_SLVSBB4.gif Figure 59. Low Dropout Operation
TPS54341 C001_SLVSC61.png Figure 61. Efficiency Versus Load Current
TPS54341 C003_SLVSC61.png Figure 63. Efficiency Versus Load Current
TPS54341 C005_SLVSC61.png Figure 65. Overall Loop Frequency Response
TPS54341 C007_SLVSC61.png Figure 67. Regulation Versus Input Voltage
TPS54341 ac_G002_lvsBK0.gif Figure 50. Line Transient (8 V to 40 V)
TPS54341 scope_starup_en_slvsc61.gif Figure 52. Startup With EN
TPS54341 ac_G006_lvsBK0.gif Figure 54. Output Ripple DCM
TPS54341 ac_G008_lvsBK0.gif Figure 56. Input Ripple CCM
TPS54341 ac_G010_lvsbb4.gif Figure 58. Low Dropout Operation
TPS54341 G023_SLVSBB4.gif Figure 60. Low Dropout Operation
TPS54341 C002_SLVSC61.png Figure 62. Light Load Efficiency
TPS54341 C004_SLVSC61.png Figure 64. Light Load Efficiency
TPS54341 C006_SLVSC61.png Figure 66. Regulation Versus Load Current