SLVSC56B September   2013  – November 2015 TPS54540-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse-Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      10. 7.3.10 Synchronization to RT/CLK Pin
      11. 7.3.11 Maximum Switching Frequency
      12. 7.3.12 Accurate Current Limit
      13. 7.3.13 Overvoltage Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 Small Signal Model for Loop Response
      16. 7.3.16 Simple Small Signal Model for Peak Current Mode Control
      17. 7.3.17 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter With 6-V to 42-V Input and 3.3-V at 5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Selecting the Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection (LO)
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Catch Diode
          5. 8.2.1.2.5  Input Capacitor
          6. 8.2.1.2.6  Bootstrap Capacitor Selection
          7. 8.2.1.2.7  Undervoltage Lockout Set Point
          8. 8.2.1.2.8  Output Voltage and Feedback Resistors Selection
          9. 8.2.1.2.9  Compensation
          10. 8.2.1.2.10 Power Dissipation Estimate
          11. 8.2.1.2.11 Safe Operating Area
          12. 8.2.1.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output
      3. 8.2.3 Split-Rail Power Supply
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54540-Q1 device is a 42-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 5 A. Example applications are: 12-V and 24-V industrial, automotive, and communications power systems. Use the following design procedure to select component values for the TPS54540-Q1 device. This procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors. Calculations can be done with the excel spreadsheet (SLVC452) located on the product page. Alternately, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.

8.2 Typical Applications

8.2.1 Buck Converter With 6-V to 42-V Input and 3.3-V at 5-A Output

TPS54540-Q1 schematic_lvsc56.gif Figure 34. 3.3-V Output TPS54540 Design Example

8.2.1.1 Design Requirements

This guide illustrates the design of a high-frequency switching regulator using ceramic output capacitors. A few parameters must be known to start the design process. These requirements are typically determined at the system level. This example in Figure 34 is designed with the known parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE
Output Voltage 3.3 V
Transient Response 1.25-A to 3.75-A load step ΔVOUT = 4 %
Maximum Output Current 5 A
Input Voltage 12 V nom. 6 V to 42 V
Output Voltage Ripple 0.5% of VOUT
Start Input Voltage (rising VIN) 5.75 V
Stop Input Voltage (falling VIN) 4.5 V

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Selecting the Switching Frequency

The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest switching frequency possible because this produces the smallest solution size. High switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage and the frequency foldback protection.

Equation 8 and Equation 9 should be used to calculate the upper limit of the switching frequency for the regulator (see Equation 24 and Equation 25). Choose the lower value result from the two equations. Switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit.

The typical minimum on time, tonmin, is 135 ns for the TPS54540-Q1 device. Equation 8 and Equation 9 should be used to calculate the upper limit of the switching for the regulator (see Equation 24 and Equation 25). For this example, the output voltage is 3.3 V and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52 V, inductor DC resistance of 10.3 mΩ, typical switch resistance of 92-mΩ and 5-A load, from Equation 8 the maximum switch frequency to avoid pulse skipping is 680 kHz. To ensure overcurrent runaway is not a concern during short circuits use Equation 9 to determine the maximum switching frequency for frequency foldback protection. With a current limit value of 6.3 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 960 kHz.

For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated maximums. To determine the timing resistance for a given switching frequency, use Equation 6 or the curve in Equation 6. The switching frequency is set by resistor R3 shown in Figure 34. For 400-kHz operation, the closest standard value resistor is 243 kΩ (see Equation 26).

Equation 24. TPS54540-Q1 q_23_lvsBx7.gif
Equation 25. TPS54540-Q1 q_24_lvsBx7.gif
Equation 26. TPS54540-Q1 q_25_lvsBN0.gif

8.2.1.2.2 Output Inductor Selection (LO)

To calculate the minimum value of the output inductor, use Equation 27.

KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer, however, the following guidelines may be used.

For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable. When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple current. This provides sufficient ripple current with the input voltage at the minimum.

For this design example, KIND = 0.3 and the inductor value is calculated to be 5.1 μH. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 29 and Equation 30 (using Equation 28). For this design, the RMS inductor current is 5 A and the peak inductor current is 5.79 A. The chosen inductor is a WE 744325550, which has a saturation current rating of 12 A and an RMS current rating of 10 A. This conductor also has a typical inductance of 5.5 µH at no load and 4.8 µH at a 5-A load. Lastly, the chosen conductor has a DCR of 10.3 mΩ.

As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the TPS54540 device, which is nominally 7.5 A.

Equation 27. TPS54540-Q1 q_26_lvsBx7.gif

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Equation 28. TPS54540-Q1 q_27_lvsBx7.gif

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Equation 29. TPS54540-Q1 q_28_lvsBx7.gif

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Equation 30. TPS54540-Q1 q_29_lvsBx7.gif

8.2.1.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the increased load current until the regulator responds to the load step. A regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. Equation 31 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore, ΔIOUT is 3.75 A – 1.25 A = 2.5 A and ΔVOUT = 0.04 × 3.3 V = 0.13 V. Using these numbers gives a minimum capacitance of 95 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.

The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is shown in Figure 39. The excess energy absorbed in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 32 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the peak output voltage, and Vi is the initial voltage. For this example, the worst case load step will be from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum in our specification is 4 % of the output voltage. This makes Vf = 1.04 × 3.3 V = 3.43 V. Vi is the initial capacitor voltage that is the nominal output voltage of 3.3 V. Using these numbers in Equation 32 yields a minimum capacitance of 68 μF.

Equation 33 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the inductor ripple current. Equation 33 yields 30 μF.

Equation 34 calculates the maximum ESR an output capacitor must meet the output voltage ripple specification. Equation 34 indicates the equivalent ESR should be less than 10 mΩ.

The most stringent criteria for the output capacitor is 95 μF required to maintain the output voltage within regulation tolerance during a load transient.

Capacitance deratings for aging, temperature and Eco-mode bias increases this minimum value. For this example, 2 × 100-μF, 6.3-V type X5R ceramic capacitors with 2 mΩ of ESR will be used. The derated capacitance is 130 µF, well above the minimum required capacitance of 95 µF.

Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability, especially non ceramic capacitors. Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 35 can be used to calculate the RMS ripple current that the output capacitor must support. For this example, Equation 35 yields 460 mA.

Equation 31. TPS54540-Q1 q_30_lvsBx7.gif
Equation 32. TPS54540-Q1 q_31_lvsBx7.gif
Equation 33. TPS54540-Q1 q_32_lvsBx7.gif
Equation 34. TPS54540-Q1 q_33_lvsBx7.gif
Equation 35. TPS54540-Q1 q_34_lvsBx7.gif

8.2.1.2.4 Catch Diode

The TPS54540 device requires an external catch diode between the SW pin and GND. The selected diode must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of 42-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54540-Q1 device.

For the example design, the PDS760-13 Schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the PDS760-13 is 0.52 V at
5 A and 25°C.

The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 36 is used to calculate the total power dissipation, including conduction losses and AC losses of the diode.

The PDS760-13 diode has a junction capacitance of 300 pF. Using Equation 36, the total loss in the diode at the nominal input voltage is 1.9 W.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode, which has a low leakage current and slightly higher forward voltage drop.

Equation 36. TPS54540-Q1 q_35_lvsBx7.gif

8.2.1.2.5 Input Capacitor

The TPS54540-Q1 device requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance includes any loss of capacitance due to DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54540-Q1 device. The input ripple current can be calculated using Equation 37.

The value of a ceramic capacitor varies significantly with temperature and the Eco-mode bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the DC bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support transients up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V. For this example, four 4.7-μF, 50-V capacitors in parallel are used. Table 2 lists several choices of high voltage capacitors.

The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage ripple occurs at 50% duty cycle and can be calculated using Equation 38. Using the design example values,
IOUT = 5 A, CIN = 18.8 μF, ƒsw = 400 kHz, yields an input voltage ripple of 170 mV and a rms input ripple current of 2.5 A.

Equation 37. TPS54540-Q1 q_36_lvsBx7.gif
Equation 38. TPS54540-Q1 q_37_lvsBx7.gif

Table 2. Capacitor Types

VENDOR VALUE (μF) EIA SIZE VOLTAGE DIALECTRIC COMMENTS
Murata 1 to 2.2 1210 100 V X7R GRM32 series
1 to 4.7 50 V
1 1206 100 V GRM31 series
1 to 2.2 50 V
Vishay 1 to 1.8 2220 50 V VJ X7R series
1 to 1.2 100 V
1 to 3.9 2225 50 V
1 to 1.8 100 V
TDK 1 to 2.2 1812 100 V C series C4532
1.5 to 6.8 50 V
1 to 2.2 1210 100 V C series C3225
1 to 3.3 50 V
AVX 1 to 4.7 1210 50 V X7R dielectric series
1 100 V
1 to 4.7 1812 50 V
1 to 2.2 100 V

8.2.1.2.6 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10-V or higher voltage rating.

8.2.1.2.7 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54540-Q1device. The UVLO has two thresholds, one for power-up when the input voltage is rising and one for power-down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage is greater than 5.75 V (UVLO start). After the regulator starts switching, it should continue to do so until the input voltage falls below 4.5 V (UVLO stop).

Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For the example application, a 365 kΩ between VIN and EN (RUVLO1) and a 88.7 kΩ between EN and ground (RUVLO2) are required to produce the 5.75-V and 4.5-V start and stop voltages.

Equation 39. TPS54540-Q1 q_38_lvsBx7.gif
Equation 40. TPS54540-Q1 q_39_lvsBx7.gif

8.2.1.2.8 Output Voltage and Feedback Resistors Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6. Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher resistor values decreases quiescent current and improves efficiency at low-output currents but may also introduce noise immunity problems. For more details about adjusting the output voltage, see Equation 41.

Equation 41. TPS54540-Q1 q_Rhs_Rls_lvsbx7.gif

8.2.1.2.9 Compensation

There are several methods to design compensation for DC-DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole.

To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 42 and Equation 43. For COUT, use a derated value of 130 μF. Use equations Equation 44 and Equation 45 to estimate a starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1850 Hz and ƒz(mod) is 610 kHz. Equation 43 is the geometric mean of the modulator pole and the ESR zero and Equation 45 is the mean of modulator pole and half of the switching frequency. Equation 44 yields 34 kHz and Equation 45 gives 19 kHz. Use the geometric mean value of Equation 44 and Equation 45 for an initial crossover frequency. For this example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved transient response.

Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

Equation 42. TPS54540-Q1 q_41_lvsBx7.gif
Equation 43. TPS54540-Q1 q_42_lvsBx7.gif
Equation 44. TPS54540-Q1 q_43_lvsBx7.gif
Equation 45. TPS54540-Q1 q_44_lvsBx7.gif

To determine the compensation resistor, R4, use Equation 46. The typical power stage transconductance, gmps, is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V,
0.8 V and 350 μA/V, respectively. R4 is calculated to be 17 kΩ and a standard value of 16.9 kΩ is selected. Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 5100 pF for compensating capacitor C5. 4700 pF is used for this design.

Equation 46. TPS54540-Q1 q_46_lvsbx7.gif
Equation 47. TPS54540-Q1 q_C5_lvsBx7.gif

A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 48 and Equation 49 for C8 to set the compensation pole. The selected value of C8 is 47 pF for this design example.

Equation 48. TPS54540-Q1 q_48_lvsBx7.gif
Equation 49. TPS54540-Q1 q_49_lvsBx7.gif

8.2.1.2.10 Power Dissipation Estimate

The formulas in Equation 50 and Equation 56 show how to estimate the TPS54540-Q1 power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is operating in discontinuous conduction mode (DCM).

The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design example.

Equation 50. TPS54540-Q1 q_50_lvsBN0.gif

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Equation 51. TPS54540-Q1 q_51_lvsBN0.gif

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Equation 52. TPS54540-Q1 q_52_lvsBN0.gif

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Equation 53. TPS54540-Q1 q_pq_lvsb44.gif

where

  • IOUT is the output current (A)
  • RDS(on) is the on-resistance of the high-side MOSFET (Ω)
  • VOUT is the output voltage (V)
  • VIN is the input voltage (V)
  • fsw is the switching frequency (Hz)
  • trise is the SW pin voltage rise time and can be estimated by trise = VIN × 0.16 ns/V + 3 ns
  • QG is the total gate charge of the internal MOSFET
  • IQ is the operating nonswitching supply current

Therefore,

Equation 54. TPS54540-Q1 q_54_lvsBN0.gif

For given TA,

Equation 55. TPS54540-Q1 q_tj_lvs795.gif

For given TJMAX = 150°C

Equation 56. TPS54540-Q1 q_tamax_lvs795.gif

where

  • Ptot is the total device power dissipation (W)
  • TA is the ambient temperature (°C)
  • TJ is the junction temperature (°C)
  • RTH is the thermal resistance of the package (°C/W)
  • TJMAX is maximum junction temperature (°C)
  • TAMAX is maximum ambient temperature (°C)

There will be additional power losses in the regulator circuit due to the inductor AC and Eco-mode losses, the catch diode and PCB trace resistance impacting the overall efficiency of the regulator.

8.2.1.2.11 Safe Operating Area

The safe operating area (SOA) of the device is shown in Figure 35, through Figure 38 for 3.3-V, 5-V, and 12-V outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at which the TPS54540-Q1 device is at or below the maximum operating temperature. The device is soldered directly to the EVM, which is a 4-layer double-sided PCB with 2-oz. copper. Careful attention must be paid to the other components chosen for the design, especially the catch diode.

TPS54540-Q1 C047_SLVSC56.png Figure 35. 3.3-V Outputs
TPS54540-Q1 C049_SLVSC56.png Figure 37. 12-V Outputs
TPS54540-Q1 C048_SLVSC56.png Figure 36. 5-V Outputs
TPS54540-Q1 C050_SLVSC56.png Figure 38. Air Flow Conditions
VIN = 36 V, VO = 12 V

8.2.1.2.12 Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current is less than 560 mA. The power supply enters Eco-mode when the output current is lower than 18 mA. The input current draw is 240 μA with no load.

8.2.1.3 Application Curves

Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted.
TPS54540-Q1 fig036_lvsbx7.gif
Figure 39. Load Transient
TPS54540-Q1 fig038_lvsbx7.gif
Figure 41. Start-Up With VIN
TPS54540-Q1 fig040_lvsbx7.gif
Figure 43. Output Ripple CCM
TPS54540-Q1 fig042_lvsbx7.gif
Figure 45. Output Ripple PSM
TPS54540-Q1 fig044_lvsbx7.gif
Figure 47. Input Ripple DCM
TPS54540-Q1 G022_SLVSBB4.gif
Figure 49. Low Dropout Operation
TPS54540-Q1 C048_SLVSBX7.png
Figure 51. Efficiency vs Load Current
TPS54540-Q1 C050_SLVSBX7.png
Figure 53. Efficiency vs Load Current
TPS54540-Q1 C052_SLVSBX7.png
Figure 55. Efficiency vs Output Current
TPS54540-Q1 C054_SLVSBX7.png
Figure 57. Regulation vs Load Current
TPS54540-Q1 fig037_lvsbx7.gif
Figure 40. Line Transient (8 V to 40 V)
TPS54540-Q1 fig039_lvsbx7.gif
Figure 42. Start-Up With EN
TPS54540-Q1 fig041_lvsbx7.gif
Figure 44. Output Ripple DCM
TPS54540-Q1 fig043_lvsbx7.gif
Figure 46. Input Ripple CCM
TPS54540-Q1 fig045_lvsbx7.gif
Figure 48. Low Dropout Operation
TPS54540-Q1 G023_SLVSBB4.gif
Figure 50. Low Dropout Operation
TPS54540-Q1 C049_SLVSBX7.png
Figure 52. Light Load Efficiency
TPS54540-Q1 C051_SLVSBX7.png
Figure 54. Light Load Efficiency
TPS54540-Q1 C053_SLVSBX7.png
Figure 56. Overall Loop Frequency Response
TPS54540-Q1 C055_SLVSBX7.png
Figure 58. Regulation vs Input Voltage

8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output

The TPS54540-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and negative voltage power supply. For a more detailed example, see SLVA317.

TPS54540-Q1 sch_lvsbn0.gif Figure 59. TPS54540-Q1 Inverting Power Supply from SLVA317 Application Note

8.2.3 Split-Rail Power Supply

The TPS54540-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and negative voltage power supply. For a more detailed example, see SLVA369.

TPS54540-Q1 split_rail_lvsbn0.gif Figure 60. TPS54540-Q1 Split Rail Power Supply Based on the SLVA369 Application Note