JAJSGT7B May   2013  – January 2019 TPS55330

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション(昇圧)
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
      2. 7.3.2 Switching Frequency
      3. 7.3.3 Overcurrent Protection and Frequency Foldback
        1. 7.3.3.1 Minimum On-Time and Pulse Skipping
      4. 7.3.4 Voltage Reference and Setting Output Voltage
      5. 7.3.5 Soft-Start
      6. 7.3.6 Slope Compensation
      7. 7.3.7 Enable and Thermal Shutdown
      8. 7.3.8 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI < 2.9 V (Minimum VI)
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Operation at Light Loads
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency (R4)
        3. 8.2.2.3  Determining the Duty Cycle
        4. 8.2.2.4  Selecting the Inductor (L1)
        5. 8.2.2.5  Computing the Maximum Output Current
        6. 8.2.2.6  Selecting the Output Capacitor (C8-C10)
        7. 8.2.2.7  Selecting the Input Capacitors (C2, C7)
        8. 8.2.2.8  Setting Output Voltage (R1, R2)
        9. 8.2.2.9  Setting the Soft-start Time (C7)
        10. 8.2.2.10 Selecting the Schottky Diode (D1)
        11. 8.2.2.11 Compensating the Control Loop (R3, C4, C5)
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.6 Selecting the Output Capacitor (C8-C10)

At least 4.7 µF of ceramic type X5R or X7R capacitance is recommended at the output. The output capacitance is mainly selected to meet the requirements for the output ripple (VRIPPLE) and voltage change during a load transient. Then the loop is compensated for the output capacitor selected. The output capacitance should be chosen based on the most stringent of these criteria. The output ripple voltage is related to the capacitance and equivalent series resistance (ESR) of the output capacitor. Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by Equation 18. If high ESR capacitors are used it will contribute additional ripple. The maximum ESR for a specified ripple is calculated with Equation 19. ESR ripple can be neglected for ceramic capacitors but must be considered if tantalum or electrolytic capacitors are used. The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated by the Equation 20. Equation 21 can be used to calculate the RMS current that the output capacitor needs to support.

Equation 18. TPS55330 eq18_Cout_lvsbd4.gif
Equation 19. TPS55330 eq19_esr_lvsbx8.gif
Equation 20. TPS55330 eq20_Cout_lvsbd4.gif
Equation 21. TPS55330 eq21_ICOrms_lvsbd4.gif

Using Equation 18 for this design, the minimum output capacitance for the specified 25 mV output ripple is
66 µF. For a maximum transient voltage change (ΔVTRAN) of 200 mV with a 1 mA load transient (ΔITRAN) and a
10 kHz control loop bandwidth (fBW) with Equation 20, the minimum output capacitance is 84 µF. The most stringent criteria is the 66 µF for the required load transient. Equation 21 gives a 2 A RMS current in the output capacitor. The capacitor should also be properly rated for the desired output voltage.

Care must be taken when evaluating ceramic capacitors that derate under dc bias, aging and AC signal conditions. For example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the range of converter switching frequency. Self-resonance causes the effective capacitance to be significantly lower. The DC bias can also significantly reduce capacitance. Ceramic capacitors can lose as much as 50% of the capacitance whan operated at the rated voltage. Therefore, allow margin in selected capacitor voltage rating to ensure adequate capacitance at the required output voltage. For this example, two 47 µF, 16 V 1210 X5R ceramic capacitors are used in parallel leading to a negligible ESR. Choosing 16 V capacitors instead of 6.3 V reduces the effects of DC bias and allows this example circuit to be rated for the maximum output voltage range of the TPS55330.