JAJSEQ9E November   2013  – December 2017 TPS56520 , TPS56720 , TPS56920 , TPS56C20

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 List of Devices
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PWM Operation
      2. 9.3.2 PWM Frequency and Adaptive On-Time Control
      3. 9.3.3 VIN and Power VIN Terminals (VIN and PVIN)
      4. 9.3.4 Auto-Skip Eco-mode™ Control
      5. 9.3.5 Soft Start and Pre-Biased Soft Start
      6. 9.3.6 Power Good
      7. 9.3.7 Overcurrent Protection
      8. 9.3.8 UVLO Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation at Light Loads
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
      2. 9.5.2 I2C Protocol
      3. 9.5.3 I2C Chip Address Byte
    6. 9.6 Register Maps
      1. 9.6.1 I2C Register Address Byte
      2. 9.6.2 Output Voltage Registers
      3. 9.6.3 CheckSum Bit (VOUT Register Only)
      4. 9.6.4 Control Registers
      5. 9.6.5 Latchoff
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Output Voltage Resistors Selection
            1. 10.2.1.2.1.1 Output Filter Selection
          2. 10.2.1.2.2 Input Capacitor Selection
          3. 10.2.1.2.3 Bootstrap Capacitor Selection
          4. 10.2.1.2.4 VREG5 Capacitor Selection
      2. 10.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves
      3. 10.2.3 TPS56C20 12-A Converter
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Design Procedure
        3. 10.2.3.3 TPS56C20 Application Performance Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|20
サーマルパッド・メカニカル・データ
発注情報

9.6.4 Control Registers

There are 4 control registers: Registers 0, 8, 9 and 24.

Table 3. Summary of Default Control Bits

CONTROL BIT(s) DEFAULT
(BINARY)		 FUNCTION
VOUT[7:0] 0110010 VOUT code, 7 bits VOUT[6:0] + odd parity checksum bit at VOUT[7]
Writing a valid code to this register also sets Internal Mode.
Sending an invalid code (checksum incorrect) to this register does not change register contents or set Internal/Enable bits.
Internal Mode 0
(EXTERNAL mode)		 1. If set to 1, the part switches to INTERNAL mode and VOUT register value controls output voltage.
2. Writing a valid code to the VOUT register sets this Internal Mode bit to 1.
3. The part can be set back to EXTERNAL control mode at any time by writing this bit to 0.
PGOOD Delay [1:0] 11 Part defaults to PGOOD Delay = 26.4µS
Hiccup Mode 1 Part defaults to Hiccup Mode On. If Hiccup Mode is enabled, do not turn on OVP Latchoff Mode and/or UVP Latchoff Mode.
ECO Mode 0 Part defaults to ECO Mode Off
DAC Settle [1:0] 11 Part defaults to DAC Settle = 25µS
Enable 0 Part defaults to Disabled.
This bit can be set to 1 by writing the bit to 1. The external EN terminal being set to 1 overrides the register value (you cannot disable the part by writing a 0 if the EN terminal is high).
OVP Latchoff Mode Disable 1 Part defaults to Latchoff Mode Off. If Hiccup Mode is enabled, do not turn on OVP Latchoff Mode and/or UVP Latchoff Mode.
UVP Latchoff Mode Disable 1 Part defaults to Latchoff Mode Off. If Hiccup Mode is enabled, do not turn on OVP Latchoff Mode and/or UVP Latchoff Mode.
CurLim[2:0] 111 Selects default current limit value

Enable: This bit can be used to enable the regulator just like setting the EN terminal high. The EN terminal has priority (if EN=high, the Enable bit does nothing, the chip is already enabled). This allows the customer to tie EN to GND externally or leave the EN terminal floating (the terminal is pulled low internally) and subsequently enable the regulator by I2C software control.

DAC Settle [1:0]: When a new VOUT voltage is selected, this happens by setting an internal DAC to a new internal VREF voltage. If this happens instantly, the regulator loop will be thrown out of regulation and the DCAP2 loop must respond to bring the VOUT back into regulation at its new chosen value. This can cause VOUT overshoots (or undershoots) or head to high transient input currents. Therefore, an analog filter on the DAC output causes this internal VREF to change more slowly. The DAC Settle[1:0] bits change the filter time constant as follows:

DAC Settle [1:0] Typical Filter Time Constant
00 6 µs
01 10 µs
10 15 µs
11 25 µs

The power-up default value of the DAC Settle[1:0] bits is 11.

Internal Mode: This bit can be interrogated to discover whether the chip is running in EXT Mode (using external resistor dividers to VFB terminal to set the output voltage) or INT Mode (using codes set in Output Voltage register to set the output voltage). Further, it can be set by the user to force either Internal or External mode. Writing a valid value to a VOUT register always sets External to 1 on the corresponding regulator.

In default, the TPS56X20 will start up into external mode and the output voltage is set by VFB with divider resistors. If starting up into internal VID mode is desired, the input voltage should be applied first, write Internal Mode bit to "1" the next, then enable the device by EN terminal or EN bit.

Current Limit [2:0]: Set the low-side valley current limit threshold for the regulator. Power-up default setting is [111].

TPS56520 TPS56720 TPS56920 TPS56C20
Current Limit [2:0] Typical Current Limit Typical Current Limit Typical Current Limit Typical Current Limit Units
000 1.72 3 3.8 5.08 Amps
001 2.28 3.6 4.76 6.16 Amps
010 2.88 4.58 5.8 7.68 Amps
011 3.44 5.52 6.88 9.12 Amps
100 4.32 6.68 8.52 11.16 Amps
101 5.32 8.24 10.32 13.44 Amps
110 6.4 9.92 12.52 16.24 Amps
111 7.84 12.12 15.16 19.76 Amps

PGOOD Delay [1:0]: Especially for low load currents, large jumps in the I2C-controlled VOUT setting may have a long settling time compared to the UV/OV thresholds. If this happens, it will cause the PGOOD signal to temporarily indicate a fault condition. If this is not the desired behavior, it is possible to “blank” the PGOOD being pulled down for some number of µS according to the table below.

PGOOD Delay [1:0] FUNCTION
00 Set delay from PGOOD fault to PGOOD terminal pulldown to 0µS
01 Set delay from PGOOD fault to PGOOD terminal pulldown to 6.6µS
10 Set delay from PGOOD fault to PGOOD terminal pulldown to 13.2µS
11 Set delay from PGOOD fault to PGOOD terminal pulldown to 26.4µS (Default)

On power-up, the delay defaults to 26.4 µS. The user can reset the blanking time using these codes at any time without affecting any other device behavior.