SLVS451G September   2003  – December 2014 TPS61020 , TPS61024 , TPS61025 , TPS61026 , TPS61027 , TPS61028 , TPS61029

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Typical Schematic
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Controller Circuit
      2. 10.3.2 Synchronous Rectifier
      3. 10.3.3 Down Regulation
      4. 10.3.4 Device Enable
      5. 10.3.5 Undervoltage Lockout
      6. 10.3.6 Softstart and Short Circuit Protection
      7. 10.3.7 Low Battery Detector Circuit—LBI/LBO
      8. 10.3.8 Low-EMI Switch
    4. 10.4 Device Functional Modes
      1. 10.4.1 Undervoltage Lockout
      2. 10.4.2 Power Save Mode
    5. 10.5 Programming
      1. 10.5.1 Programming the Output Voltage
      2. 10.5.2 Programming the LBI/LBO Threshold Voltage
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Inductor Selection
        2. 11.2.2.2 Input Capacitor Selection
        3. 11.2.2.3 Output Capacitor Selection
      3. 11.2.3 Application Curves
    3. 11.3 System Examples
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
    2. 14.2 Related Links
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ

13 Layout

13.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. The most critical current path for all boost converters is from the switching FET, through the synchronous FET, then the output capacitors, and back to ground of the switching FET. Therefore, both output capacitors and their traces should be placed on the same board layer as close as possible between the IC’s VOUT and PGND pin. Especially at output voltages above 4.5 V, adding an RC snubber from the SW pin to PGND pin may assist in further reducing the parasitic inductance impact of this critical current path. Refer to the application report (SLVA255) for details of implementing a snubber. In addition, the input capacitor should be placed as close as possible between the IC’s VBAT and PGND pin. Placing the inductor close to the SW pin with a wide but short trace helps to improve efficiency and minimize EMI. To lay out the control ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids ground shift problems that can occur due to superimposition of power ground current and control ground current. The recommended layout is shown in Layout Example.

13.2 Layout Example

TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 TPS61029_layout_update.gifFigure 28. PCB Layout Recommendation

13.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below.

  • Improving the power dissipation capability of the PCB design
  • Improving the thermal coupling of the component to the PCB
  • Introducing airflow in the system

The maximum recommended junction temperature (TJ) of the TPS6102x devices is 125°C. The thermal resistance of the 10-pin VSON 3 × 3 package (DRC) is RΘJA = 47.2°C/W, if the PowerPAD is soldered. Specified regulator operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 847 mW. More power can be dissipated if the maximum ambient temperature of the application is lower.

Equation 8. TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 Q_PDmax_lvs451.gif