JAJSJ29D May   2020  – October 2021 TPS61378-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VCC Power Supply
      2. 8.3.2  Input Undervoltage Lockout (UVLO)
      3. 8.3.3  Enable and Soft Start
      4. 8.3.4  Shut Down
      5. 8.3.5  Switching Frequency Setting
      6. 8.3.6  Spread Spectrum Frequency Modulation
      7. 8.3.7  Adjustable Peak Current Limit
      8. 8.3.8  Bootstrap
      9. 8.3.9  Load Disconnect
      10. 8.3.10 MODE/SYNC Configuration
      11. 8.3.11 Overvoltage Protection (OVP)
      12. 8.3.12 Output Short Protection/Hiccup
      13. 8.3.13 Power-Good Indicator
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced PWM Mode
      2. 8.4.2 Auto PFM Mode
      3. 8.4.3 External Clock Synchronization
      4. 8.4.4 Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Setting the Switching Frequency
        3. 9.2.2.3 Setting the Current Limit
        4. 9.2.2.4 Selecting the Inductor
        5. 9.2.2.5 Selecting the Output Capacitors
        6. 9.2.2.6 Selecting the Input Capacitors
        7. 9.2.2.7 Loop Stability and Compensation
          1. 9.2.2.7.1 Small Signal Model
          2. 9.2.2.7.2 Loop Compensation Design Steps
          3. 9.2.2.7.3 Selecting the Bootstrap Capacitor
          4. 9.2.2.7.4 VCC Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.4 Down Mode

The TPS61378-Q1 features down mode operation when input voltage is close to or higher than output voltage. In down mode, output voltage is regulated at target value, even when VIN > VO. The TPS61378-Q1 high-side and low-side FETs are switching devices that always work in boost operation, where the isolation FET always works as a linear device.

For boost circuits, on-time or duty cycle is reduced as input voltage approaches output voltage. The TPS61378-Q1 enters down mode when VIN reaches 85% (typical) of VO voltage at 2.2 MHz. Exiting down mode requires VIN to be reduced below 85% (typical) of VO voltage at 2.2 MHz.

In normal operation, the isolation FET is fully on.

When down mode is triggered and VIN is less than VO pin voltage, the OUT pin has a fixed 2 V (typical) above VO pin voltage. An isolation FET works in LDO mode to regulate VO pin voltage with a 2-V constant voltage drop.

When down mode is triggered and VIN is 100 mV (typical) higher than VO pin voltage, the OUT pin has an approximated 3 V (typical) above the VIN pin voltage. As VIN keeps rising, the OUT pin continues rising with 3 V on top of VIN. In addition, an isolation FET works in LDO mode to regulate VO pin voltage with a voltage differential of the OUT pin and VO pin.

Refer to Figure 8-1.

GUID-20200915-CA0I-BMQV-ML4D-2SNRCPV8CVPG-low.gif Figure 8-1 Down Mode

Take care during short-to-ground condition when operation VIN is above 6 V. During hiccup on, the device operates in down mode and the isolation FET voltage drop is VIN + 3 V (OUT pin to VO pin).