JAJSJ29E May   2020  – October 2024 TPS61378-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC Power Supply
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
      3. 7.3.3  Enable and Soft Start
      4. 7.3.4  Shut Down
      5. 7.3.5  Switching Frequency Setting
      6. 7.3.6  Spread Spectrum Frequency Modulation
      7. 7.3.7  Adjustable Peak Current Limit
      8. 7.3.8  Bootstrap
      9. 7.3.9  Load Disconnect
      10. 7.3.10 MODE/SYNC Configuration
      11. 7.3.11 Overvoltage Protection (OVP)
      12. 7.3.12 Output Short Protection/Hiccup
      13. 7.3.13 Power-Good Indicator
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced PWM Mode
      2. 7.4.2 Auto PFM Mode
      3. 7.4.3 External Clock Synchronization
      4. 7.4.4 Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming the Output Voltage
        2. 8.2.2.2 Setting the Switching Frequency
        3. 8.2.2.3 Setting the Current Limit
        4. 8.2.2.4 Selecting the Inductor
        5. 8.2.2.5 Selecting the Output Capacitors
        6. 8.2.2.6 Selecting the Input Capacitors
        7. 8.2.2.7 Loop Stability and Compensation
          1. 8.2.2.7.1 Small Signal Model
          2. 8.2.2.7.2 Loop Compensation Design Steps
          3. 8.2.2.7.3 Selecting the Bootstrap Capacitor
          4. 8.2.2.7.4 VCC Capacitor
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 用語集
    6. 11.6 静電気放電に関する注意事項
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.7 Adjustable Peak Current Limit

The TPS61378-Q1 adopts a cycle-by-cycle peak current limit internally and changes its current limit with different working conditions. The low-side switch is turned off immediately as soon as the switch peak current triggers the peak current limit. The peak switch current limit can be set by a resistor from the ILIM pin to ground. The relationship between the peak current limit and the resistor is shown in Equation 2.

Equation 2. TPS61378-Q1

where

  • RILIM is the resistance between the ILIM pin and the GND. This pin cannot be left floating or connected to VCC.
  • ILIM is switch peak current limit

For instance, the current limit is set to 4.8 A if the RLIM is 20 kΩ.

Table 7-1 summarizes the peak current limit under various conditions. The current limit applies to the start-up phase.

Table 7-1 Switch Peak Current Limit
Behavior Switch Peak Current Limit
Vin < VO (Not in Down Mode) ILIM(1)
Vin < VO (In Down Mode) 2/3 ILIM
3V > Vin - VO > 0V 4/9 ILIM
6V > Vin - VO > 3V 1/4 ILIM
Vin - VO > 6V 1/4 ILIM & Fsw Clamp to 1.1MHz if FREQ pin setting is > 1.1MHz
FB ≤ 0.1V 1/5 ILIM & Fsw Clamp to 1.1MHz if FREQ pin setting is > 1.1MHz
(1) ILIM is switch peak current limit programmed in Equation 2.