JAJSNC4A november   2021  – may 2023 TPS62441 , TPS62442

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. Parameter Measurement Information
    1. 8.1 Schematic
  10. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable (EN)
      2. 9.3.2 COMP/FSET
      3. 9.3.3 MODE/SYNC
      4. 9.3.4 Undervoltage Lockout (UVLO)
      5. 9.3.5 Power-Good Output (PG)
      6. 9.3.6 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short-Circuit Protection
      5. 9.4.5 Output Discharge
      6. 9.4.6 Soft Start
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 External Component Selection
        1. 10.1.2.1 Inductor Selection
        2. 10.1.2.2 Capacitor Selection
          1. 10.1.2.2.1 Input Capacitor
          2. 10.1.2.2.2 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

GUID-DC001C3A-AC08-44C5-86AC-87F38212ED4E-low.gifFigure 6-1 14-Pin QFN RQR Package Top View
Table 6-1 Pin Functions
PINI/ODESCRIPTION
NAMENO.
EN18IThis pin is the enable pin of converter 1. Connect to logic low to disable the device. Pull high to enable the device. Do not leave this pin unconnected.
EN210IThis pin is the enable pin of converter 2. Connect to logic low to disable the device. Pull high to enable the device. Do not leave this pin unconnected.
FB13IVoltage feedback input for converter 1. Connect the resistive output voltage divider to this pin.
FB21IVoltage feedback input for converter 2. Connect the resistive output voltage divider to this pin.
PG14OOpen-drain power-good output of converter 1
PG213OOpen-drain power-good output of converter 2
SW16This pin is the switch pin of converter 1 and is connected to the internal power MOSFETs.
SW212This pin is the switch pin of converter 2 and is connected to the internal power MOSFETs.
MODE/SYNC5IThe device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high, the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can also be used to synchronize the device to an external frequency. See the electrical characteristics for the detailed specification for the digital signal applied to this pin for external synchronization.
COMP/FSET14IDevice compensation and frequency set input. A resistor from this pin to GND defines the compensation of the control loop as well as the switching frequency if not externally synchronized. Do not leave this pin floating.
VIN17Power supply input. Make sure the input capacitor is connected as close as possible between pin VIN1 and GND. Connect VIN1 to VIN2.
VIN211Power supply input. Make sure the input capacitor is connected as close as possible between pin VIN2 and GND. Connect VIN2 to VIN1.
GND2, 9Ground pins. The GND pins are internally connected.