SLVSFU1B April   2023  – October 2023 TPS62874-Q1 , TPS62875-Q1 , TPS62876-Q1 , TPS62877-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6.   Device Options
  7. Pin Configuration and Functions
  8. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - Q100
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  9. Parameter Measurement Information
  10. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS-Control Topology
      2. 8.3.2  Forced-PWM and Power-Save Modes
      3. 8.3.3  Transient Non-Synchronous Mode (optional)
      4. 8.3.4  Precise Enable
      5. 8.3.5  Start-Up
      6. 8.3.6  Switching Frequency Selection
      7. 8.3.7  Output Voltage Setting
        1. 8.3.7.1 Output Voltage Range
        2. 8.3.7.2 Output Voltage Setpoint
        3. 8.3.7.3 Non-Default Output Voltage Setpoint
        4. 8.3.7.4 Dynamic Voltage Scaling
        5. 8.3.7.5 Droop Compensation
      8. 8.3.8  Compensation (COMP)
      9. 8.3.9  Mode Selection / Clock Synchronization (MODE/SYNC)
      10. 8.3.10 Spread Spectrum Clocking (SSC)
      11. 8.3.11 Output Discharge
      12. 8.3.12 Undervoltage Lockout (UVLO)
      13. 8.3.13 Overvoltage Lockout (OVLO)
      14. 8.3.14 Overcurrent Protection
        1. 8.3.14.1 Cycle-by-Cycle Current Limiting
        2. 8.3.14.2 Hiccup Mode
        3. 8.3.14.3 Current-Limit Mode
      15. 8.3.15 Power Good (PG)
        1. 8.3.15.1 Standalone / Primary Device Behavior
        2. 8.3.15.2 Secondary Device Behavior
      16. 8.3.16 Remote Sense
      17. 8.3.17 Thermal Warning and Shutdown
      18. 8.3.18 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
      6. 8.5.6 Dynamic Voltage Scaling (DVS)
    6. 8.6 Device Registers
  11. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Selecting the Input Capacitors
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor CC
        6. 9.2.2.6 Selecting the Compensation Capacitor CC2
      3. 9.2.3 Application Curves
    3. 9.3 Application Using Two TPS62876-Q1 in a Stacked Configuration
      1. 9.3.1 Design Requirements For Two Stacked Devices
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Compensation Resistor
        2. 9.3.2.2 Selecting the Output Capacitors
        3. 9.3.2.3 Selecting the Compensation Capacitor CC
      3. 9.3.3 Application Curves for Two Stacked Devices
    4. 9.4 Application Using Three TPS62876-Q1 in a Stacked Configuration
      1. 9.4.1 Design Requirements For Three Stacked Devices
      2. 9.4.2 Detailed Design Procedure
        1. 9.4.2.1 Selecting the Compensation Resistor
        2. 9.4.2.2 Selecting the Output Capacitors
        3. 9.4.2.3 Selecting the Compensation Capacitor CC
      3. 9.4.3 Application Curves for Three Stacked Devices
    5. 9.5 Best Design Practices
    6. 9.6 Power Supply Recommendations
    7. 9.7 Layout
      1. 9.7.1 Layout Guidelines
      2. 9.7.2 Layout Example
  12. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  13. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Selecting the Output Capacitors

In practice, the total output capacitance typically comprises a combination of different capacitors, in which larger capacitors provide the load current at lower frequencies and smaller capacitors provide the load current at higher frequencies. The value, type, and location of the output capacitors are critical for correct operation. TI recommends low-ESR multilayer ceramic capacitors with an X7R dielectric (or similar) for best performance.

The TPS6287x-Q1 devices feature a butterfly layout with two GND pins on opposite sides of the package. This allows the output capacitors to be placed symmetrically on the PCB such that the electromagnetic fields generated cancel each other out, thereby reducing EMI.

The transient response of the converter is defined by one of two criteria:

  • The loop bandwidth, which must be at least 4 times smaller than the switching frequency.
  • The slew rate of the current through the inductor and the output capacitance.

    In typical low-output-voltage application, this is limited by the value of the output voltage and the inductors.

Which of the above criteria applies in any given application depends on the operating conditions and component values used. We therefore recommend calculating the output capacitance for both cases, and selecting the higher of the two values.

If the converter remains in regulation, the minimum output capacitance required is given by:

Equation 14. COUT(min)(reg)=τ×gm×RZ2×π×L×fSW41+TOLIND2+TOLfSW2
Equation 15. COUT(min)(reg)=12.5×10-6×1.5×10-3×1.8×1032×π×80×10-9×2.25×10641+20%2+10%2F=146 μF

If the converter loop saturates, the minimum output capacitance is given by:

Equation 16. COUT(min)(sat)=1VOUTL×IOUT+IL(PP)222×VOUT  IOUT×tt21+TOLIND
Equation 17. COUT(min)(sat)=118.75×10380×109×7.5+3.22222×0.75  7.5×1×10621+20%F =43 μF

In this case, choose COUT(min) = 146 μF, as the larger of the two values, for the output capacitance.

When calculating worst-case component values, use the value calculated above as the minimum output capacitance required. For ceramic capacitors, the nominal capacitance when considering tolerance, DC bias, temperature, and aging effects is typically two times the minimum capacitance. In this case the nominal capacitance is thus 292 μF.

Table 9-4 List of Recommended Output Capacitors
CAPACITANCEDIMENSIONSVOLTAGE RATINGMANUFACTURER, PART NUMBER
mm (inch)
22 μF ±20%2012 (0805)6.3 VTDK, CGA4J1X7T0J226M125AC
22 μF ±10%2012 (0805)6.3 VMurata, GCM31CR71A226KE02
47 μF ±20%3216 (1206)4 VTDK, CGA5L1X7T0G476M160AC
47 μF ±20%3225 (1210)6.3 VMurata, GCM32ER70J476ME19
100 μF ±20%3225 (1210)4 VTDK, CGA6P1X7T0G107M250AC
100 μF ±20%3216 (1210)6.3 VMurata, GRT32EC70J107ME13